-
1.发明授权公开(公告)号：US11159172B2
公开(公告)日：2021-10-26
申请号：US17019749
申请日：2020-09-14
Applicant: Shenzhen Goodix Technology Co., Ltd.
Inventor： Shuo Fan
Abstract: A capacitive analog-to-digital converter, an analog-to-digital conversion system, a chip, and a device. The capacitive analog-to-digital converter includes: a first capacitor array, including N first capacitor banks that include M first capacitors, where M is a positive integer greater than N; M first switches, respectively connected to first electrode plates of the M first capacitors in a one-to-one correspondence to enable a successive approximation logic controller to control connections of the first electrode plates of the M first capacitors with an output of a voltage generation circuit and with a first sampling voltage output by controlling the M first switches; a comparator, including a first input, a second input and an output; and the successive approximation logic controller, connected to the output of the comparator, and configured to control the M first switches according to comparison results output by the output of the comparator.
-
公开(公告)号：US10921938B2
公开(公告)日：2021-02-16
申请号：US16420146
申请日：2019-05-22
Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
Inventor： Zhengfeng Wang , Shuo Fan
Abstract: A capacitance detecting circuit, includes a first front end circuit, a second front end circuit, a control circuit and a processing circuit, wherein the control circuit controls the first front end circuit and the second front end circuit such that the first front end circuit is configured to convert a capacitance signal of a detection capacitor into a first voltage signal through a first calibration capacitor, and the second front end circuit is configured to convert a capacitance signal of the detection capacitor into a second voltage signal through a second calibration capacitor; the processing circuit is calculates a differential signal of the first voltage signal and the second voltage signal to determine a capacitance variation of the detection capacitor according to the differential signal.
-
公开(公告)号：US10079609B2
公开(公告)日：2018-09-18
申请号：US15784514
申请日：2017-10-16
Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
Inventor： Shuo Fan
Abstract: This disclosure discloses a DAC capacitor array, which includes a plurality of sub-capacitor arrays that are connected in parallel. Each sub-capacitor array includes: a capacitor group, including N capacitors connected in parallel, N being a positive integer; and a primary switch and a plurality of multiplexers; wherein one terminal of each capacitor in the capacitor group is connected to an input terminal of a comparator, and is connected to an input source via the primary switch; and the other terminals of the capacitors in the capacitor group are connected to a plurality of input sources via corresponding multiplexers respectively. The DAC capacitor array is optimized by adjusting the reference voltage to which the capacitors in the DAC capacitor array are connected, which reduces the overall capacitance of the DAC capacitor array.
-
公开(公告)号：US11481072B2
公开(公告)日：2022-10-25
申请号：US17019573
申请日：2020-09-14
Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
Inventor： Shuo Fan
Abstract: Provided is a capacitance detection circuit, which has better detection performance. The capacitance detection circuit includes: a first charging and discharging circuit configured to perform charging or discharging on a capacitor to be detected; a second charging and discharging circuit configured to perform charging or discharging on a calibration capacitor; an analog-to-digital conversion circuit configured to continuously sample a voltage difference between the capacitor to be detected and the calibration capacitor in a charging or discharging process to obtain sampled data; and a digital processing circuit configured to detect a capacitance of the capacitor to be detected according to the sampled data.
-
公开(公告)号：US10411725B2
公开(公告)日：2019-09-10
申请号：US16168774
申请日：2018-10-23
Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
Inventor： Shuo Fan
Abstract: An analog-to-digital conversion circuit and method are provided. At a sampling stage, the first capacitor array connects lower electrode plates of N capacitors to a first input voltage, connect lower electrode plates of the other capacitors to a common-mode voltage, and connect upper electrode plates of all the capacitors to the common-mode voltage to sample the first input voltage; in an ith conversion at a conversion stage, the logic circuit controls, the lower electrode plate of an ith capacitor to connect to a reference voltage or a ground voltage, a first comparison voltage output by the first capacitor array approximates a second comparison voltage; and the comparator stores a comparison result between the first and the second comparison voltage to an i+1th flag bit in the logic circuit, and analog-to-digital conversion is completed when i+1 is equal to the total number of capacitors in the first capacitor array.
-
Patent Agency Ranking
公开(公告)号：US10382053B2
公开(公告)日：2019-08-13
申请号：US16119739
申请日：2018-08-31
Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
Inventor： Shuo Fan
Abstract: A capacitive successive approximation analog-to-digital converter is provided, where the capacitive successive approximation analog-to-digital converter includes a first capacitor array including N first capacitors; a second capacitor array including N second capacitors; a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage; a first switch, a second switch, N third switches and N fourth switches; a comparator including a first input end, a second input end and an output end, where upper plates of the N first capacitors are connected to the first input end and upper plates of the N second capacitors are connected to the second input end; and a successive approximation logic controller connected to the output end of the comparator. The capacitive successive approximation analog-to-digital converter in the above technical solution can use 2N capacitors to implement outputting an N-bit binary code.
-
公开(公告)号：US10372284B2
公开(公告)日：2019-08-06
申请号：US15879760
申请日：2018-01-25
Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
Inventor： Shuo Fan
Abstract: The present disclosure relates to a capacitance variation detection circuit, a touch screen and a touch detection method. The method includes: connecting one terminal of a detection capacitor and one terminal of a denoising capacitor to a first power simultaneously, and connecting the other terminal of the detection capacitor and the other terminal of a denoising capacitor to a reference ground simultaneously; disconnecting the detection capacitor from the first power source and connecting it to the negative input terminal of the operation amplifier, switching the one terminal of the denosing capacitor from being connected to the first power source to being connected to the reference ground, and connecting the other terminal of the denoising capacitor to the negative input terminal of the operational amplifier; and acquiring an output result of the operational amplifier, and judging whether there is a touch operation according to the output result.
-
8.发明申请公开(公告)号：US20180091163A1
公开(公告)日：2018-03-29
申请号：US15827179
申请日：2017-11-30
Applicant: SHENZHEN GOODIX TECHNOLOGY CO. , LTD.
Inventor： Shuo Fan
IPC: H03M1/00
Abstract: The present disclosure relates to a method for reducing power consumption, including: connecting one terminal of each capacitor in a first and a second capacitor array of an SAR ADC to a first reference voltage via a corresponding primary switch, connecting the other terminal of the capacitors to a positive-terminal analog input signal and a negative-terminal analog input signal respectively via a corresponding multiplexer to complete sampling; determining a value of a most-significant bit by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array, maintaining or adjusting a reference voltage connected to the other terminal of each capacitor according to the value of the most-significant bit, and determining values of a second-most-significant bit and a least-significant bit by comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array.
-
公开(公告)号：US10693423B2
公开(公告)日：2020-06-23
申请号：US16147857
申请日：2018-09-30
Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
Inventor： Shuo Fan
Abstract: A dynamic amplification circuit includes a first drive circuit (310) generates a first driving voltage according to a first control signal and a first driving current; a second drive circuit (320) generates a first driving signal according to the first and a second driving voltage; a third drive circuit (330) generates a second control signal according to the first control signal and the first driving signal; and a dynamic amplifier DA (340) includes a first branch (101) including a first capacitor and a second branch (102) including a second capacitor which are connected by a first resistor (150) and a second resistor (160), an operation state of the DA (340) is controlled through the first and second control signals, a duration of the DA (340) in an amplification phase is proportional to a product of a resistance value of the first resistor and a capacitance value of the first capacitor.
-
公开(公告)号：US10476443B2
公开(公告)日：2019-11-12
申请号：US16110127
申请日：2018-08-23
Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
Inventor： Shuo Fan
Abstract: The present disclosure discloses a dynamic amplification circuit, including: a first drive circuit, receives a first control signal to generate a first and a second voltage signal; a second drive circuit, receives the first and the second voltage signal to generate a first drive signal; a third drive circuit, receives the first control signal and the first drive signal to generate a second control signal; and a dynamic amplifier DA, controls a first and a second control switch according to the control signals; in a first time period, the first control signal is high level, the second control signal is low level; in a second time period, the opposite is the case; in a third time period, the first and the second control signal are both at low level, a duration of the second time period is inversely proportional to a transconductance of a transistor in a saturation region.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.047 seconds)
