公开(公告)号：US20230122734A1

公开(公告)日：2023-04-20

申请号：US17906984

申请日：2021-03-24

申请人： SHENZHEN PANGO MICROSYSTEMS CO.,LTD.

发明人： Xinjian CHEN ,  Yuanjun LIANG

IPC分类号： H04L7/00 ,  H03L7/08 ,  H03L7/085

摘要： Disclosed are a clock and data recovery circuit, method and apparatus. The circuit comprises a receiving module for receiving an analog signal; a first equalization module connected to the receiving module, the first equalization module comprising a first totalizer and a second totalizer; a first sampling module connected to an output end of the first totalizer, the first sampling module comprising a first edge sampler and a second edge sampler that are connected to the output end of the first totalizer, respectively; a second sampling module connected to an output end of the second totalizer; a data processing module connected to both the first sampling module and the second sampling module; a clock recovery module connected to the data processing module; and an output module connected to the clock recovery module. In the present application, by means of the manner, a phase can be adjusted using a bias voltage, thereby accurately recovering clock information.

公开(公告)号：US20220385279A1

公开(公告)日：2022-12-01

申请号：US17775906

申请日：2020-07-20

申请人： SHENZHEN PANGO MICROSYSTEMS CO.,LTD.

发明人： Kai LI ,  Yuanjun LIANG

IPC分类号： H03K5/01 ,  H03K3/037 ,  H03K21/02

摘要： A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.