公开(公告)号：US20230402095A1

公开(公告)日：2023-12-14

申请号：US18060884

申请日：2022-12-01

Applicant: SK Hynix Inc.

Inventor： Jong Ho LEE ,  Jun Ku Ahn ,  Gwang Sun Jung ,  Uk Hwang

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: G11C13/0069 ,  H01L45/1253 ,  H01L45/144 ,  H01L27/2481

Abstract: A semiconductor memory device includes a memory cell interposed between a first electrode and a second electrode, and configured with a chalcogenide layer that includes three or more components, and a peripheral circuit for providing the memory cell with a program pulse inducing a compositional gradient in the chalcogenide layer.

公开(公告)号：US11707005B2

公开(公告)日：2023-07-18

申请号：US16855760

申请日：2020-04-22

Applicant: SK hynix Inc.

Inventor： Gwang Sun Jung ,  Sang Hyun Ban ,  Jun Ku Ahn ,  Beom Seok Lee ,  Young Ho Lee ,  Woo Tae Lee ,  Jong Ho Lee ,  Hwan Jun Zang ,  Sung Lae Cho ,  Ye Cheon Cho ,  Uk Hwang

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00

CPC classification number: H10N70/8825 ,  G11C13/003 ,  H10B63/24 ,  H10N70/841

Abstract: A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 13 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 13 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 13 element.