公开(公告)号：US10995401B2

公开(公告)日：2021-05-04

申请号：US16510274

申请日：2019-07-12

Applicant: SK hynix Inc.

Inventor： Jun Ku Ahn

IPC: H01J37/34 ,  C23C14/34 ,  C23C14/06 ,  C23C14/54 ,  B23P15/26

Abstract: A sputtering target includes: a base configured to transfer heat in a basal plane direction; and a first heat sink disposed on a sidewall of the base, the first heat sink configured to transfer heat along a direction that is different from the basal plane direction.

公开(公告)号：US11581486B2

公开(公告)日：2023-02-14

申请号：US16940060

申请日：2020-07-27

Applicant: SK hynix Inc.

Inventor： Jun Ku Ahn

IPC: H01L45/00

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed at intersection regions of the first lines and the second lines between the first lines and the second lines in a third direction perpendicular to the first and second directions; and a heat sink positioned between two memory cells adjacent to each other in a diagonal direction with respect to the first and second directions.

公开(公告)号：US11974442B2

公开(公告)日：2024-04-30

申请号：US17234483

申请日：2021-04-19

Applicant: SK hynix Inc.

Inventor： Hyung Keun Kim ,  Jun Ku Ahn ,  Jun Young Lim ,  Sung Lae Cho

IPC: H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N70/00

CPC classification number: H10B63/845 ,  H10B61/00 ,  H10N50/01 ,  H10N70/023 ,  H10N70/823 ,  H10B61/10 ,  H10B63/24

Abstract: A semiconductor device includes a stack structure including first electrodes and insulating layers alternately stacked on each other, a second electrode passing through the stack structure, and variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes. Each of the first electrodes includes a first sidewall facing the second electrode, and each of the insulating layers includes a second sidewall facing the second electrode. At least a part of each of the variable resistance patterns protrudes farther towards the second electrode than the second sidewall.

公开(公告)号：US11968912B2

公开(公告)日：2024-04-23

申请号：US17324833

申请日：2021-05-19

Applicant: SK hynix Inc.

Inventor： Jun Ku Ahn

IPC: H10B63/00 ,  C23C14/06 ,  C23C14/34 ,  H10N70/00

CPC classification number: H10N70/026 ,  C23C14/0623 ,  C23C14/3414 ,  H10B63/00 ,  H10N70/8828

Abstract: A sputtering target and a method for fabricating an electronic device using the same are provided. A sputtering target may include a carbon-doped GeSbTe alloy, wherein, for the carbon-doped GeSbTe alloy, an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 μm to 5 μm, and a first ratio of an average grain diameter of carbon after the sintering is Y (μm) to the average grain diameter of the GeSbTe alloy after the sintering may be in a range of greater than 0.5 and equal to or less than 1.5. Alternatively, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) may be satisfied, where an average grain diameter of a GeSbTe alloy after sintering is X (μm), an average grain diameter of carbon after the sintering is Y (μm), and a content of carbon is Z (at %).

公开(公告)号：US20230402095A1

公开(公告)日：2023-12-14

申请号：US18060884

申请日：2022-12-01

Applicant: SK Hynix Inc.

Inventor： Jong Ho LEE ,  Jun Ku Ahn ,  Gwang Sun Jung ,  Uk Hwang

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: G11C13/0069 ,  H01L45/1253 ,  H01L45/144 ,  H01L27/2481

Abstract: A semiconductor memory device includes a memory cell interposed between a first electrode and a second electrode, and configured with a chalcogenide layer that includes three or more components, and a peripheral circuit for providing the memory cell with a program pulse inducing a compositional gradient in the chalcogenide layer.

公开(公告)号：US11707005B2

公开(公告)日：2023-07-18

申请号：US16855760

申请日：2020-04-22

Applicant: SK hynix Inc.

Inventor： Gwang Sun Jung ,  Sang Hyun Ban ,  Jun Ku Ahn ,  Beom Seok Lee ,  Young Ho Lee ,  Woo Tae Lee ,  Jong Ho Lee ,  Hwan Jun Zang ,  Sung Lae Cho ,  Ye Cheon Cho ,  Uk Hwang

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00

CPC classification number: H10N70/8825 ,  G11C13/003 ,  H10B63/24 ,  H10N70/841

Abstract: A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 13 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 13 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 13 element.