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    Power saving techniques that use a lower bound on bit errors
    1.
    发明授权
    Power saving techniques that use a lower bound on bit errors 有权
    使用位错误下限的省电技术

    公开(公告)号：US09128710B2

    公开(公告)日：2015-09-08

    申请号：US13902410

    申请日：2013-05-24

    申请人： SK hynik memory solutions inc.

    发明人： Arunkumar Subramanian ,  Frederick K. H. Lee ,  Jason Bellorado ,  Xiangyu Tang ,  Lingqi Zeng

    IPC分类号： G06F1/32 ,  G11C7/00

    CPC分类号： G06F1/3206 ,  G06F1/32 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G11C7/00 ,  Y02D10/13 ,  Y02D10/14

    摘要： A read back bit sequence and charge constraint information are obtained. A lower bound on a number of bit errors associated with the read back bit sequence is determined based at least in part on the read back bit sequence and the charge constraint information. The lower bound and an error correction capability threshold associated with an error correction decoder are compared. In the event the lower bound is greater than or equal to the error correction capability threshold, an error correction decoding failure is predicted and in response to the prediction a component is configured to save power.

    摘要翻译： 获得回读比特序列和电荷约束信息。 至少部分地基于回读比特序列和电荷约束信息来确定与回读比特序列相关联的多个比特错误的下限。 比较与纠错解码器相关联的下限和纠错能力阈值。 在下限大于或等于纠错能力阈值的情况下，预测出纠错解码失败，并且响应于该预测，将部件配置为节省功率。