公开(公告)号：US10970208B2

公开(公告)日：2021-04-06

申请号：US16232248

申请日：2018-12-26

Applicant: SK hynix Inc.

Inventor： Seung-Gyu Jeong ,  Su-Hae Woo ,  Chang-Soo Ha

IPC: G06F12/0802 ,  G06F3/06

Abstract: A memory system includes a memory device including a main memory and a cache memory that includes a plurality of cache lines for caching data stored in the main memory, wherein each of the cache lines includes cache data, a valid bit indicating whether or not the corresponding cache data is valid, and a loading bit indicating whether or not read data of the main memory is being loaded; and a memory controller suitable for scheduling an operation of the memory device with reference to the valid bits and the loading bits.

公开(公告)号：US10713137B2

公开(公告)日：2020-07-14

申请号：US15980275

申请日：2018-05-15

Applicant: SK hynix Inc.

Inventor： Hyun-Seok Kim ,  Jae-Won Han ,  Chang-Soo Ha

IPC: G06F11/00 ,  G06F11/20 ,  G11C29/52 ,  G06F11/10 ,  G11C29/44 ,  G11C29/00 ,  G11C8/12

Abstract: A memory module includes: a plurality of first memory ranks that belong to a first group; a plurality of second memory ranks that belong to a second group; and a rank mapping circuit suitable for mapping a defective first memory rank among the first memory ranks to a defect-free second memory rank among the second memory ranks.