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    Memory module and operation method of the same
    3.
    发明授权
    Memory module and operation method of the same 有权

    公开(公告)号：US10713114B2

    公开(公告)日：2020-07-14

    申请号：US15897265

    申请日：2018-02-15

    Applicant: SK hynix Inc.

    Inventor： Hyun-Seok Kim

    IPC: G06F11/00 ,  G06F11/10 ,  G06F12/084 ,  G06F3/06 ,  G11C29/52

    Abstract: A memory module includes a plurality of main memory groups each suitable for storing user data and related ECC data; a cache memory group suitable for caching the user data of one among the main memory groups; an access controller suitable for accessing the main memory groups when user data to be accessed is not cached in the cache memory group; and an ECC unit suitable for performing an ECC operation for user data stored or to be stored in the main memory groups during an access operation for the user data stored or to be stored in the main memory groups.

    Reservoir capacitor and semiconductor device including the same
    4.
    发明授权
    Reservoir capacitor and semiconductor device including the same 有权
    蓄电池电容器和包括其的半导体器件

    公开(公告)号：US09276500B2

    公开(公告)日：2016-03-01

    申请号：US14106792

    申请日：2013-12-15

    Applicant: SK hynix Inc.

    Inventor： Boo-Ho Jung ,  Sung-Woo Han ,  Ic-Su Oh ,  Jun-Ho Lee ,  Hyun-Seok Kim ,  Sun-Ki Cho ,  Tae-Hoon Kim ,  Ki-Chul Hong

    IPC: G11C11/401 ,  H02M11/00 ,  G11C5/06 ,  G11C5/14 ,  G11C7/02 ,  G11C11/4074

    CPC classification number: H02M11/00 ,  G11C5/063 ,  G11C5/14 ,  G11C7/02 ,  G11C11/4074

    Abstract: A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.

    Abstract translation: 蓄电池电容器包括具有两个或更多个电容器的第一电容器组，其在第一电源电压端子和第二电源电压端子之间彼此串联耦合，第二电容器组具有两个或更多个电容器，其串联耦合 在第三电源电压端子与第四电源电压端子之间相互连接的第二电容器组和适于将第一电容器组的电容器之间的第一耦合节点电耦合到第二电容器组的电容器之间的第二耦合节点的连接线 。

    Memory system and memory module
    5.
    发明授权
    Memory system and memory module 有权

    公开(公告)号：US11249844B2

    公开(公告)日：2022-02-15

    申请号：US16668740

    申请日：2019-10-30

    Applicant: SK hynix Inc.

    Inventor： Young-Ook Song ,  Hyun-Seok Kim

    IPC: G06F11/10

    Abstract: A memory system includes: an error correction code generation circuit suitable for generating an error correction code including one or more symbols for write data including a plurality of symbols, to output a codeword including the write data and the error correction code; a first data mapping circuit suitable for mapping the symbols of the codeword to a dataword; and a memory suitable for storing the dataword.

    Memory module
    6.
    发明授权
    Memory module 有权

    公开(公告)号：US10593374B2

    公开(公告)日：2020-03-17

    申请号：US15724354

    申请日：2017-10-04

    Applicant: SK hynix Inc.

    Inventor： Hyun-Seok Kim

    IPC: G11C5/04 ,  G11C7/22 ,  G06F13/16 ,  G11C29/04

    Abstract: A memory module includes a front side interface configured to serial-to-parallel convert a command, an address, and data, based on a host clock, and transfer the converted command, address, and data; a processing block configured to operate in synchronization with a division clock, process the command, address, and data transferred from the front side interface, and transfer the processed command, address, and data; a back side interface configured to include a PLL for generating a media clock having a frequency different from the host clock, to parallel-to-serial convert the command, address, and data transferred from the processing block, based on the media clock, and to transfer the converted command, address, and data; and memory devices configured to operate in synchronization with the media clock, and to write the data transferred from the back side interface therein in response to the command and address transferred from the back side interface.

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