公开(公告)号：US10332585B2

公开(公告)日：2019-06-25

申请号：US15685182

申请日：2017-08-24

Applicant: SK hynix Inc.

Inventor： Jung Hwan Lee ,  Dae Yong Shim ,  Kang Seol Lee

IPC: H03K19/094 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/08 ,  G11C11/4074

Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.

公开(公告)号：US10388401B2

公开(公告)日：2019-08-20

申请号：US15480798

申请日：2017-04-06

Applicant: SK hynix Inc.

Inventor： Min Seok Choi ,  Dae Yong Shim

IPC: G11C29/52 ,  H03M13/29 ,  G06F11/10

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a command and an address, and inputting/outputting data. The semiconductor system may include a second semiconductor device including first and second registers, wherein first corrected data, which is generated by correcting an error of internal data outputted in a first error correction operation, may be stored in the first register, and second corrected data, which is generated by correcting an error of the internal data outputted in a second error correction operation, may be stored in the second register, based on the command and the address.

公开(公告)号：US10290333B2

公开(公告)日：2019-05-14

申请号：US15612150

申请日：2017-06-02

Applicant: SK hynix Inc.

Inventor： Seol Hee Lee ,  Chang Hyun Kim ,  Dae Yong Shim ,  Kang Seol Lee

IPC: G11C29/00 ,  G11C7/22 ,  G06F11/10 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C29/04

Abstract: A semiconductor device includes an internal operation control circuit suitable for generating a set period signal which is enabled for a set period, in response to a write command and an internal operation control signal, and generating a column select signal, an output control signal and an input control signal in response to the set period signal; and an internal operation circuit suitable for performing an internal operation of converting parity data generated from input data and storing the converted parity data in a memory cell array, in response to the column select signal, the output control signal and the input control signal.

公开(公告)号：US10580480B2

公开(公告)日：2020-03-03

申请号：US16441945

申请日：2019-06-14

Applicant: SK hynix Inc.

Inventor： Jung Hwan Lee ,  Dae Yong Shim ,  Kang Seol Lee

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/08 ,  G11C11/4074

Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.