公开(公告)号：US10290333B2

公开(公告)日：2019-05-14

申请号：US15612150

申请日：2017-06-02

Applicant: SK hynix Inc.

Inventor： Seol Hee Lee ,  Chang Hyun Kim ,  Dae Yong Shim ,  Kang Seol Lee

IPC: G11C29/00 ,  G11C7/22 ,  G06F11/10 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C29/04

Abstract: A semiconductor device includes an internal operation control circuit suitable for generating a set period signal which is enabled for a set period, in response to a write command and an internal operation control signal, and generating a column select signal, an output control signal and an input control signal in response to the set period signal; and an internal operation circuit suitable for performing an internal operation of converting parity data generated from input data and storing the converted parity data in a memory cell array, in response to the column select signal, the output control signal and the input control signal.

公开(公告)号：US10332585B2

公开(公告)日：2019-06-25

申请号：US15685182

申请日：2017-08-24

Applicant: SK hynix Inc.

Inventor： Jung Hwan Lee ,  Dae Yong Shim ,  Kang Seol Lee

IPC: H03K19/094 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/08 ,  G11C11/4074

Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.

公开(公告)号：US09236295B2

公开(公告)日：2016-01-12

申请号：US14013932

申请日：2013-08-29

Applicant: SK hynix Inc.

Inventor： Young Hee Yoon ,  Kang Seol Lee

IPC: G01R31/26 ,  G01R1/06 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L21/66 ,  H01L23/48 ,  G11C5/04 ,  G11C8/12 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/76877 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  H01L22/32 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544

Abstract: Provided is a semiconductor apparatus in which a plurality of semiconductor chips stacked in a vertical direction. Each of the semiconductor chips comprises: a bank area comprising a plurality of banks configured to store data; and a peripheral area including a pad area in which a plurality of pads configured to receive signals for controlling the bank area and a plurality of TSV for electrically connecting the plurality of pads, respectively.

Abstract translation: 提供一种半导体装置，其中多个半导体芯片沿垂直方向堆叠。 每个半导体芯片包括：存储区域，其包括被配置为存储数据的多个存储体; 以及包括焊盘区域的周边区域，其中多个焊盘被配置为接收用于控制焊盘区域的信号，以及多个TSV，用于电连接多个焊盘。

公开(公告)号：US10580480B2

公开(公告)日：2020-03-03

申请号：US16441945

申请日：2019-06-14

Applicant: SK hynix Inc.

Inventor： Jung Hwan Lee ,  Dae Yong Shim ,  Kang Seol Lee

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/08 ,  G11C11/4074

Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.

公开(公告)号：US10008290B2

公开(公告)日：2018-06-26

申请号：US15492493

申请日：2017-04-20

Applicant: SK hynix Inc.

Inventor： Seol Hee Lee ,  Kang Seol Lee

IPC: G11C29/00 ,  G11C17/16 ,  G11C8/10

CPC classification number: G11C29/76 ,  G11C8/10 ,  G11C8/12 ,  G11C17/16 ,  G11C29/78 ,  G11C2029/4402

Abstract: A repair control device for memory cells divided into a plurality of banks may include a failed address storage circuit configured to sort and store a plurality of failed addresses each containing a failed bank address and a failed row address, according to the failed row address, and store the failed row address by matching the failed row address with total failed bank information representing one or more failed banks indicated by the failed row address. The repair control device also includes an address comparison circuit configured to compare an input address to a pair comprised of the failed row address and the total failed bank information, stored in the failed address storage circuit, and generate a hit signal based on the comparison result. The repair control device further includes an address generation circuit configured to generate an access target address based on the hit signal.

公开(公告)号：US08866521B2

公开(公告)日：2014-10-21

申请号：US14158391

申请日：2014-01-17

Applicant: SK hynix Inc.

Inventor： Kang Seol Lee ,  Jae Hyuk Im

IPC: H03L7/06 ,  G11C11/4074 ,  G11C5/14 ,  H03L5/00

CPC classification number: G11C5/14 ,  G11C5/145 ,  G11C11/4074 ,  H03L5/00

Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.