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公开(公告)号：US20200257473A1
公开(公告)日：2020-08-13
申请号：US16858414
申请日：2020-04-24
Applicant: SK hynix Inc.
Inventor： Chang Hyun KIM , Eui Cheol LIM , Young Jung CHOI , Hyung Sik WON , Sun Woong KIM
Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.
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公开(公告)号：US20200034699A1
公开(公告)日：2020-01-30
申请号：US16519643
申请日：2019-07-23
Applicant: SK hynix Inc.
Inventor： Jae Hyeok JANG , Joo Young KIM , Eui Cheol LIM
Abstract: An accelerating apparatus for a neural network may include: an input processor configured to decide a computation mode according to precision of an input signal, and change or maintain the precision of the input signal according to the decided computation mode; and a computation circuit configured to receive the input signal from the input processor, perform select one or more operations among multiple operations including a multiplication based on the input signal, boundary migration to rearrange multiple signals divided from the input signal, and an addition of the input signal subjected to the boundary migration, according to the computation mode, and perform the selected one or more operations on the input signal.
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公开(公告)号：US20200026669A1
公开(公告)日：2020-01-23
申请号：US16367700
申请日：2019-03-28
Applicant: SK hynix Inc.
Inventor： Sun Woong KIM , Eui Cheol LIM
Abstract: A memory system is disclosed, which relates to technology for an accelerator of a high-capacity memory device. The memory system includes a plurality of memories configured to store data therein, and a pooled memory controller (PMC) configured to perform map computation by reading the data stored in the plurality of memories and storing resultant data produced by the map computation in the plurality of memories.
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公开(公告)号：US20190266123A1
公开(公告)日：2019-08-29
申请号：US16210418
申请日：2018-12-05
Applicant: SK hynix Inc.
Inventor： Ji Hoon NAM , Eui Cheol LIM
IPC: G06F15/167 , G06F9/48 , G06F9/54 , G06F12/1072
Abstract: A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.
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公开(公告)号：US20220245066A1
公开(公告)日：2022-08-04
申请号：US17727600
申请日：2022-04-22
Applicant: SK hynix Inc.
Inventor： Mi Seon HAN , Myoung Seo KIM , Yun Jeong MUN , Eui Cheol LIM
IPC: G06F12/0882 , G06F12/1009 , G06F12/02 , G06F13/16 , G06F11/30
Abstract: A memory system includes a first memory device having a first memory that includes a plurality of access management regions and a first access latency, each of the access management regions including a plurality of pages, the first memory device configured to detect a hot access management region having an access count that reaches a preset value from the plurality of access management regions, and detect one or more hot pages included in the hot access management region; and a second memory device having a second access latency that is different from the first access latency of the first memory device. Data stored in the one or more hot pages is migrated to the second memory device.
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Patent Agency Ranking
公开(公告)号：US20210271600A1
公开(公告)日：2021-09-02
申请号：US16917460
申请日：2020-06-30
Applicant: SK hynix Inc.
Inventor： Jung Min CHOI , Byung Il KOH , Eui Cheol LIM
IPC: G06F12/0862
Abstract: A data storage device may include: a first memory configured to store a plurality of instructions and data required during an application operation; a cache configured to read, from the first memory, first data for operating the application and store the read first data therein; a processor configured to propagate a data read request to the first cache, a prefetcher, or both when a pointer chasing instruction is generated or a cache miss for the first cache occurs while the processor reads one or more instructions of the plurality of instructions and executes an application; and the prefetcher configured to read second data associated with the pointer chasing instruction or the cache miss from the first memory, and propagate the read second data to the cache.
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公开(公告)号：US20210117131A1
公开(公告)日：2021-04-22
申请号：US17134117
申请日：2020-12-24
Applicant: SK hynix Inc.
Inventor： Chang Hyun KIM , Eui Cheol LIM , Young Jung CHOI , Hyung Sik WON , Sun Woong KIM
Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.
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公开(公告)号：US20220188243A1
公开(公告)日：2022-06-16
申请号：US17543481
申请日：2021-12-06
Applicant: SK hynix Inc.
Inventor： Sung Woo HYUN , Hyeong Tak JI , Myoung Seo KIM , Jae Hoon KIM , Eui Cheol LIM
IPC: G06F12/10
Abstract: A memory module may include J memory chips configured to input/output data in response to each of a plurality of translated address signals; and an address remapping circuit configured to generate a plurality of preliminary translated address signals by adding first correction values to a target address signal provided from an exterior of the memory module, and to generate the plurality of translated address signals by shifting all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string.
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公开(公告)号：US20220147274A1
公开(公告)日：2022-05-12
申请号：US17319840
申请日：2021-05-13
Applicant: SK hynix Inc.
Inventor： Jae Hoon KIM , Eui Cheol LIM
IPC: G06F3/06 , G11C11/406 , G11C11/4076
Abstract: A storage device includes: a memory device including memory cells for storing data, the memory cells grouped into a plurality of memory banks; and a memory controller coupled in communication with the memory device and configured to provide commands to the memory device and access one or more memory banks based on address information associated with the commands. The memory controller may count a number of access times that the memory controller has accessed to first memory bank by increasing the number of access times to the first memory bank based on a time interval between first active command and second active command for the first memory bank, and transmit, to the memory device, a control signal to perform a refresh operation on the first memory bank when the number of access times counted exceeds a predetermined number.
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公开(公告)号：US20220058157A1
公开(公告)日：2022-02-24
申请号：US17510921
申请日：2021-10-26
Applicant: SK hynix Inc.
Inventor： Ji Hoon NAM , Eui Cheol LIM
IPC: G06F15/167 , G06F12/1072 , G06F9/54 , G06F9/48
Abstract: A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.
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