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    MEMORY SYSTEM
    2.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210117131A1

    公开(公告)日：2021-04-22

    申请号：US17134117

    申请日：2020-12-24

    Applicant: SK hynix Inc.

    Inventor： Chang Hyun KIM ,  Eui Cheol LIM ,  Young Jung CHOI ,  Hyung Sik WON ,  Sun Woong KIM

    IPC: G06F3/06 ,  G06F13/40

    Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.

    SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190220227A1

    公开(公告)日：2019-07-18

    申请号：US15996770

    申请日：2018-06-04

    Applicant: SK hynix Inc.

    Inventor： Chang Hyun KIM ,  Jaeil KIM

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0673

    Abstract: A semiconductor device includes an operation control circuit and a mode register activation signal generation circuit. The operation control circuit generates a chip identification storage control signal, a selection identification storage control signal, and a mode register set signal in response to an external set signal and a command. The mode register activation signal generation circuit generates a chip identification and a selection identification in response to the chip identification storage control signal and the selection identification storage control signal. The mode register activation signal generation circuit also generates a mode register activation signal for controlling a mode register set operation in response to the mode register set signal when the chip identification is identical to the selection identification.

    SEMICONDUCTOR DEVICES
    4.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20180197597A1

    公开(公告)日：2018-07-12

    申请号：US15609219

    申请日：2017-05-31

    Applicant: SK hynix Inc.

    Inventor： Chang Hyun KIM

    IPC: G11C11/406 ,  G06F11/10 ,  G11C29/52 ,  G11C11/4091 ,  G11C11/408

    CPC classification number: G11C11/40615 ,  G06F11/1068 ,  G11C11/40618 ,  G11C11/4094 ,  G11C29/52

    Abstract: A semiconductor device may be provided. The semiconductor device may include an error scrub control circuit and or an active period signal generation circuit. The error scrub control circuit may be configured to generate an error scrub pre-charge signal and an error scrub bank signal for performing an error scrub operation of memory cells included in banks, based on a bank active signal and a row address signal which are generated based on a refresh signal. The active period signal generation circuit may be configured to generate an active period signal from the bank active signal and the error scrub pre-charge signal based on the error scrub bank signal.

    DATA TRANSFER DEVICE
    9.
    发明申请
    DATA TRANSFER DEVICE 有权

    公开(公告)号：US20170153995A1

    公开(公告)日：2017-06-01

    申请号：US15066115

    申请日：2016-03-10

    Applicant: SK hynix Inc.

    Inventor： Chang Hyun KIM

    IPC: G06F13/362 ,  G06F13/40

    CPC classification number: G06F13/362 ,  G06F13/4068

    Abstract: A data transfer device includes a shifter block that generates first and second input signals and first and second output signals, an input/output control block that selects the first input signal and the first output signal in correspondence to a mode signal and outputs an input control signal and an output control signal for controlling a data input/output operation, or selects the second input signal and the second output signal and outputs the input control signal and the output control signal, and a buffer block that latches first input data or second input data which have different data bit widths according to the input control signal, and outputs first output data or second output data which have different data bit widths according to the output control signal.

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