公开(公告)号：US11443172B2

公开(公告)日：2022-09-13

申请号：US15810160

申请日：2017-11-13

申请人： SK hynix Inc.

发明人： Hyung-Dong Lee

IPC分类号： G06N3/063 ,  G06N3/04

摘要： A synapse array of a neuromorphic device is provided. The synapse array may include a pre-synaptic neuron; a row line extending from the pre-synaptic neuron in a row direction; a post synaptic neuron; a column line extending from the post-synaptic neuron in a column direction; and a synapse disposed at an intersection region between the row line and the column line. The synapse may include an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a gate electrode and a body; a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a gate electrode and a body; and a resistive element having a first node electrically connected to the source electrode of the n-FeFET and electrically connected to the source electrode of the p-FeFET, and the n-FeFET and the p-FeFET are electrically connected in series.

公开(公告)号：US11210577B2

公开(公告)日：2021-12-28

申请号：US15462696

申请日：2017-03-17

申请人： SK hynix Inc.

发明人： Hyung-Dong Lee

IPC分类号： G06N3/04 ,  G06N3/063 ,  G06N3/08

摘要： A neuromorphic device includes a pre-synaptic neuron, a synapse electrically coupled to the pre-synaptic neuron through a row line, and a post-synaptic neuron electrically coupled to the synapse through a column line. The post-synaptic neuron includes an integrator, a comparator, and an error corrector including an error detector and a correction signal generator. The comparator and the error corrector receive an output of the integrator.

公开(公告)号：US10565495B2

公开(公告)日：2020-02-18

申请号：US15389139

申请日：2016-12-22

申请人： SK hynix Inc.

发明人： Sang-Su Park ,  Hyung-Dong Lee

IPC分类号： H01L47/00 ,  G06N3/063 ,  G06N3/04

摘要： A neuromorphic device includes a synapse. The synapse includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, a reactive metal layer disposed between the oxygen-containing layer and the second electrode, and an oxygen diffusion-retarding layer disposed between the reactive metal layer and the oxygen-containing layer. The oxygen-containing layer includes a P-type material and oxygen ions. The reactive metal layer reacts with the oxygen ions of the oxygen-containing layer. The oxygen diffusion-retarding layer includes an N-type material and interferes with a movement of the oxygen ions from the oxygen-containing layer to the reactive metal layer. An interface between the oxygen-containing layer and the oxygen diffusion-retarding layer is a P-N junction.

公开(公告)号：US10418353B2

公开(公告)日：2019-09-17

申请号：US15715449

申请日：2017-09-26

申请人： SK hynix Inc.

发明人： Sang-Eun Lee ,  Hyung-Dong Lee ,  Eun Ko

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78 ,  H01L23/498 ,  H01L21/768

摘要： A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.

公开(公告)号：US10339446B2

公开(公告)日：2019-07-02

申请号：US15969680

申请日：2018-05-02

申请人： SK hynix Inc.

发明人： Hyung-Dong Lee

IPC分类号： H01L45/00 ,  G06N3/063 ,  H01L27/11519 ,  H01L27/11556 ,  G11C11/54 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/788

摘要： A neuromorphic device may include: a plurality of row lines extending in a first direction; a plurality of additional row lines extending in the first direction; a plurality of column lines extending in a second direction that crosses the first direction; and a plurality of synapses positioned at intersections of the row lines, the additional row lines, and the column lines, wherein each of the synapses includes a transistor comprising a floating gate, a control gate insulated from the floating gate, a first junction, and a second junction, the control gate being coupled to a corresponding one of the plurality of row lines, the first junction being coupled to a corresponding one of the plurality of additional row lines, the second junction being coupled to a corresponding one of the plurality of column lines.

公开(公告)号：US10199472B2

公开(公告)日：2019-02-05

申请号：US15389068

申请日：2016-12-22

申请人： SK hynix Inc.

发明人： Hyung-Dong Lee

IPC分类号： H01L29/423 ,  H01L27/105 ,  G06N3/04 ,  H01L29/66 ,  H01L29/78

摘要： A neuromorphic device includes a row line extending in a first direction; a column line disposed over the row line, the column line extending in a second direction perpendicular to the first direction; a plurality of gating lines disposed between the row line and the column line; and a synapse disposed between the row line and the column line, the synapse passing through the plurality of gating lines.

公开(公告)号：US09122598B2

公开(公告)日：2015-09-01

申请号：US13908730

申请日：2013-06-03

申请人： SK hynix Inc.

发明人： Young-Suk Moon ,  Hyung-Dong Lee ,  Yong-Kee Kwon ,  Hong-Sik Kim ,  Hyung-Gyun Yang

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F12/00 ,  G06F12/08 ,  G11C7/02 ,  G11C7/10 ,  G11C11/406 ,  G11C11/408

CPC分类号： G06F11/073 ,  G06F11/004 ,  G06F12/00 ,  G06F12/0804 ,  G06F2212/3042 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/40603 ,  G11C11/4085

摘要： A semiconductor device includes a controller configured to control a first memory device to process a request for the first memory device and a second memory device. The controller receives the request for the first memory device, determines a data damage risk of cells connected to a second signal line adjacent to a first signal line of the first memory device corresponding to a requested address by referring to information indicating a data damage risk, and stores data of the cells connected to the second signal line in the second memory device when determining that there is a data damage risk.

摘要翻译： 半导体器件包括控制器，其配置为控制第一存储器件以处理对第一存储器件和第二存储器件的请求。 控制器接收对第一存储器件的请求，通过参考指示数据损坏风险的信息，确定连接到与所请求的地址相对应的与第一存储器件的第一信号线相邻的第二信号线的单元的数据损坏风险， 并且当确定存在数据损坏风险时，将连接到第二信号线的单元的数据存储在第二存储器件中。

公开(公告)号：US11257801B2

公开(公告)日：2022-02-22

申请号：US16528938

申请日：2019-08-01

申请人： SK hynix Inc.

发明人： Sang-Eun Lee ,  Hyung-Dong Lee ,  Eun Ko

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78 ,  H01L23/498 ,  H01L21/768

摘要： A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.

公开(公告)号：US11037052B2

公开(公告)日：2021-06-15

申请号：US15388677

申请日：2016-12-22

申请人： SK hynix Inc.

发明人： Hyung-Dong Lee

IPC分类号： G06N3/063 ,  G06N3/04

摘要： A method reads data from a synapse which includes a transistor and a variable resistor. The transistor has a gate electrode, a first electrode and a second electrode. The variable resistor has a first electrode connected to the second electrode of the transistor. The method includes applying a read voltage to the gate electrode of the transistor, applying a pre-synaptic voltage to the first electrode of the transistor, and applying a post-synaptic voltage to a second electrode of the variable resistor. The read voltage is lower than the threshold voltage of the transistor.

公开(公告)号：US11017286B2

公开(公告)日：2021-05-25

申请号：US15658933

申请日：2017-07-25

申请人： SK hynix Inc.

发明人： Hyung-Dong Lee

IPC分类号： G06N3/04 ,  G06N3/063 ,  G06N3/08

摘要： A neuromorphic device may include a pre-synaptic neuron, a row line extending in a row direction from the pre-synaptic neuron, a post-synaptic neuron, a column line extending in a column direction from the post-synaptic neuron, and a synapse disposed at an intersection region between the row line and the column line. The synapse may include a first node electrically connected with the row line, a second node electrically connected with the column line, and a variable resistor and a first transistor electrically coupled between the first node and the second node. The variable resistor and the first transistor may be electrically connected with each other in parallel.