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    Semiconductor device and operating method thereof
    1.
    发明授权
    Semiconductor device and operating method thereof 有权
    半导体器件及其操作方法

    公开(公告)号：US09122598B2

    公开(公告)日：2015-09-01

    申请号：US13908730

    申请日：2013-06-03

    Applicant: SK hynix Inc.

    Inventor： Young-Suk Moon ,  Hyung-Dong Lee ,  Yong-Kee Kwon ,  Hong-Sik Kim ,  Hyung-Gyun Yang

    IPC: G06F11/00 ,  G06F11/07 ,  G06F12/00 ,  G06F12/08 ,  G11C7/02 ,  G11C7/10 ,  G11C11/406 ,  G11C11/408

    CPC classification number: G06F11/073 ,  G06F11/004 ,  G06F12/00 ,  G06F12/0804 ,  G06F2212/3042 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/40603 ,  G11C11/4085

    Abstract: A semiconductor device includes a controller configured to control a first memory device to process a request for the first memory device and a second memory device. The controller receives the request for the first memory device, determines a data damage risk of cells connected to a second signal line adjacent to a first signal line of the first memory device corresponding to a requested address by referring to information indicating a data damage risk, and stores data of the cells connected to the second signal line in the second memory device when determining that there is a data damage risk.

    Abstract translation: 半导体器件包括控制器，其配置为控制第一存储器件以处理对第一存储器件和第二存储器件的请求。 控制器接收对第一存储器件的请求，通过参考指示数据损坏风险的信息，确定连接到与所请求的地址相对应的与第一存储器件的第一信号线相邻的第二信号线的单元的数据损坏风险， 并且当确定存在数据损坏风险时，将连接到第二信号线的单元的数据存储在第二存储器件中。

    Memory system including memory controller and operation method thereof
    2.
    发明授权
    Memory system including memory controller and operation method thereof 有权

    公开(公告)号：US10140025B2

    公开(公告)日：2018-11-27

    申请号：US15270755

    申请日：2016-09-20

    Applicant: SK hynix Inc.

    Inventor： Hyung-Gyun Yang ,  Yong-Ju Kim ,  Hong-Sik Kim

    IPC: G06F3/06 ,  G06F11/10

    Abstract: A memory system may include a memory device suitable for storing data requested from a host, and a controller suitable for generating information on the data and transmitting/receiving the data and the information to/from the memory device through first and second data buses, respectively, during a first operation mode, or for transmitting/receiving the data to/from the memory device through one of the first and second data buses based on the data size, during a second operation mode.

    Semiconductor device and operating method thereof
    3.
    发明授权
    Semiconductor device and operating method thereof 有权
    半导体器件及其操作方法

    公开(公告)号：US08953393B2

    公开(公告)日：2015-02-10

    申请号：US14012008

    申请日：2013-08-28

    Applicant: SK Hynix Inc.

    Inventor： Hong-Sik Kim ,  Hyung-Dong Lee ,  Hyung-Gyun Yang

    IPC: G11C7/00 ,  G11C29/00 ,  G11C29/40 ,  G11C29/04

    CPC classification number: G11C29/00 ,  G11C29/40 ,  G11C2029/0409

    Abstract: A semiconductor device may test a semiconductor memory device by storing a data sample that is sampled from among data requested to be written into a semiconductor memory device and by comparing the data sample with data read from the semiconductor memory device which corresponds to the data sample.

    Abstract translation: 半导体器件可以通过将从被请求写入的数据中采样的数据样本存储到半导体存储器件中并通过将数据样本与对应于数据样本的半导体存储器件读取的数据进行比较来测试半导体存储器件。

    System and method for operating the same
    4.
    发明授权
    System and method for operating the same 有权

    公开(公告)号：US10339080B2

    公开(公告)日：2019-07-02

    申请号：US15188347

    申请日：2016-06-21

    Applicant: SK hynix Inc.

    Inventor： Hyung-Gyun Yang ,  Yong-Ju Kim ,  Yong-Kee Kwon ,  Hong-Sik Kim

    IPC: G06F13/28 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10

    Abstract: A system includes a central processing unit (CPU); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the CPU and the plurality of memory ports; and a memory controller suitable for, when the CPU calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.

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