公开(公告)号：US20210336132A1

公开(公告)日：2021-10-28

申请号：US17028813

申请日：2020-09-22

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Hyangkeun YOO ,  Jae Hyun HAN

IPC: H01L45/00 ,  H01L27/11502 ,  H01L27/24

Abstract: A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.

公开(公告)号：US20210175253A1

公开(公告)日：2021-06-10

申请号：US16891544

申请日：2020-06-03

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Jae Gil LEE ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

公开(公告)号：US20220278132A1

公开(公告)日：2022-09-01

申请号：US17749118

申请日：2022-05-19

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO ,  Jae Gil LEE

IPC: H01L27/11597 ,  H01L29/788 ,  H01L29/78 ,  H01L29/786 ,  H01L27/11587

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.

公开(公告)号：US20210366932A1

公开(公告)日：2021-11-25

申请号：US17075577

申请日：2020-10-20

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Kun Young LEE ,  Hyangkeun YOO

IPC: H01L27/11597 ,  H01L27/1159

Abstract: A semiconductor device according to an embodiment includes a substrate, and a gate structure disposed over the substrate. The gate structure includes a hole pattern including a central axis extending in a direction perpendicular to a surface of the substrate. The gate structure includes a gate electrode layer and an interlayer insulation layer, which are alternately stacked along the central axis. The semiconductor device includes a ferroelectric layer disposed adjacent to a sidewall surface of the gate electrode layer inside the hole pattern, and a channel layer disposed adjacent to the ferroelectric layer inside the hole pattern. In this case, one of the gate electrode layer and the interlayer insulation layer protrudes toward the central axis of the hole pattern relative to the other one of the gate electrode layer and the interlayer insulation layer.

公开(公告)号：US20210035990A1

公开(公告)日：2021-02-04

申请号：US16821186

申请日：2020-03-17

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/1159 ,  H01L27/11565 ,  H01L27/1157

Abstract: A nonvolatile memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a gate dielectric layer structure disposed on the channel layer, a ferroelectric layer disposed on the gate dielectric layer structure, and a gate electrode layer disposed on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric layer structure includes a charge tunneling layer, a charge trap layer and a charge barrier layer disposed on the channel layer.

公开(公告)号：US20230247840A1

公开(公告)日：2023-08-03

申请号：US18298167

申请日：2023-04-10

Applicant: SK hynix Inc.

Inventor： Mir IM ,  Jae Gil LEE

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: A semiconductor device according to an embodiment includes a substrate, a bit line structure and a source line structure each extending in a direction perpendicular to a surface of the substrate, a semiconductor layer disposed between the bit line structure and the source line structure on a plane parallel to the surface of the substrate, a ferroelectric layer disposed on the semiconductor layer and including a ferroelectric superlattice structure, and a gate electrode layer disposed on the ferroelectric layer.

公开(公告)号：US20220399371A1

公开(公告)日：2022-12-15

申请号：US17892514

申请日：2022-08-22

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Jae Gil LEE ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/786 ,  H01L29/78 ,  H01L29/788

Abstract: A nonvolatile memory device includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

公开(公告)号：US20220359543A1

公开(公告)日：2022-11-10

申请号：US17872838

申请日：2022-07-25

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Hyangkeun Yoo ,  Se Ho Lee

IPC: H01L27/1159 ,  H01L27/1157 ,  H01L27/11565

Abstract: A nonvolatile memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a gate dielectric layer structure disposed on the channel layer, a ferroelectric layer disposed on the gate dielectric layer structure, and a gate electrode layer disposed on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric layer structure includes a charge tunneling layer, a charge trap layer and a charge barrier layer disposed on the channel layer.

公开(公告)号：US20220189972A1

公开(公告)日：2022-06-16

申请号：US17317663

申请日：2021-05-11

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Dong Ik SUH ,  Se Ho LEE

IPC: H01L27/1159 ,  G11C11/22

Abstract: A semiconductor device according to an embodiment includes a substrate, a bit line structure and a source line structure respectively extending in a direction perpendicular to a surface of the substrate, a semiconductor layer disposed between the bit line structure and the source line structure on a plane parallel to the surface of the substrate, a first ferroelectric layer disposed on a first surface of the semiconductor layer, and a first gate electrode layer disposed on the first ferroelectric layer.

公开(公告)号：US20210175252A1

公开(公告)日：2021-06-10

申请号：US16891469

申请日：2020-06-03

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO ,  Jae Gil LEE

IPC: H01L27/11597 ,  H01L29/78 ,  H01L29/788

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.