公开(公告)号：US20240357836A1

公开(公告)日：2024-10-24

申请号：US18758786

申请日：2024-06-28

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  H10B63/82 ,  H10B63/84 ,  H10N70/24 ,  H10N70/245 ,  H10N70/253 ,  H10N70/823 ,  H10N70/841 ,  H10N70/8822 ,  H10N70/8828 ,  H10N70/883 ,  H10N70/8833 ,  H10N70/8836

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.

公开(公告)号：US20220399371A1

公开(公告)日：2022-12-15

申请号：US17892514

申请日：2022-08-22

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Jae Gil LEE ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/786 ,  H01L29/78 ,  H01L29/788

Abstract: A nonvolatile memory device includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

公开(公告)号：US20210175252A1

公开(公告)日：2021-06-10

申请号：US16891469

申请日：2020-06-03

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO ,  Jae Gil LEE

IPC: H01L27/11597 ,  H01L29/78 ,  H01L29/788

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.

公开(公告)号：US20190259778A1

公开(公告)日：2019-08-22

申请号：US16162043

申请日：2018-10-16

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO

IPC: H01L27/11597 ,  G11C5/06 ,  G11C11/22

Abstract: A ferroelectric memory device according to an embodiment includes a base conduction layer, a channel layer extending in a vertical direction from the base conduction layer, a ferroelectric layer disposed on the channel layer, a plurality of ferroelectric memory cell transistor stacked in a vertical direction on the base conduction layer, a control transistor disposed over the plurality of ferroelectric memory cell transistors, and a bit line pattern electrically connected to the channel layer.

公开(公告)号：US20190019801A1

公开(公告)日：2019-01-17

申请号：US16016603

申请日：2018-06-24

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO

IPC: H01L27/1159 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L29/78 ,  G11C11/22

Abstract: There is disclosed a method of manufacturing a ferroelectric memory device according to one embodiment. In the method, a substrate is prepared. An interfacial insulating layer is formed on the substrate. A ferroelectric material layer is formed on the interfacial insulating layer. An interfacial oxide layer including a first metal element is formed on the ferroelectric material layer. A gate electrode layer including a second metal element is formed on the interfacial oxide layer. The ferroelectric material layer and the interfacial oxide layer are subjected to a crystallization heat treatment to form a ferroelectric layer and a ferroelectric interfacial layer. The interfacial oxide layer reacts with the gate electrode layer so that the ferroelectric interfacial layer includes the first and second metal elements.

公开(公告)号：US20180277647A1

公开(公告)日：2018-09-27

申请号：US15826616

申请日：2017-11-29

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO

IPC: H01L29/51 ,  H01L29/423

CPC classification number: H01L29/513 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7923

Abstract: A nonvolatile memory device includes a semiconductor substrate, a tunnel insulation layer disposed on the semiconductor substrate, a charge trap layer disposed on the tunnel insulation layer, and a control gate electrode disposed on the charge trap layer. The tunnel insulation layer includes an antiferroelectric material.

公开(公告)号：US20210336132A1

公开(公告)日：2021-10-28

申请号：US17028813

申请日：2020-09-22

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Hyangkeun YOO ,  Jae Hyun HAN

IPC: H01L45/00 ,  H01L27/11502 ,  H01L27/24

Abstract: A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.

公开(公告)号：US20210257409A1

公开(公告)日：2021-08-19

申请号：US16941170

申请日：2020-07-28

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO

IPC: H01L27/24 ,  H01L45/00

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.

公开(公告)号：US20210202577A1

公开(公告)日：2021-07-01

申请号：US16908635

申请日：2020-06-22

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A nonvolatile memory device includes a substrate having an upper surface and a channel structure disposed over the substrate. The channel structure includes at least one channel layer pattern and at least one interlayer insulation layer pattern, which are alternately stacked in a first direction perpendicular to the upper surface, and the channel structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a resistance change layer disposed over the substrate and on at least a portion of one sidewall surface of the channel structure, a gate insulation layer disposed over the substrate and on the resistance change layer, and a plurality of gate line structures disposed over the substrate, each contacting a first surface of the gate insulation layer and disposed to be spaced apart from each other in the second direction.

公开(公告)号：US20210175253A1

公开(公告)日：2021-06-10

申请号：US16891544

申请日：2020-06-03

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Jae Gil LEE ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.