公开(公告)号：US20240320075A1

公开(公告)日：2024-09-26

申请号：US18462290

申请日：2023-09-06

申请人： SK hynix Inc.

发明人： Jae Yong SON

IPC分类号： G06F11/07 ,  G11C16/26

CPC分类号： G06F11/076 ,  G11C16/26

摘要： A semiconductor storage device searches for an optimal read voltage on the basis of an error bit variance for each second read voltage interval without performing repeated additional reads up to the limit of left and right cell difference probabilities. Accordingly, the semiconductor storage device can detect an optimal read voltage rapidly and accurately by minimizing the number of reads for a memory cell, when performing a second read for determining the optimal read voltage.

公开(公告)号：US20240211345A1

公开(公告)日：2024-06-27

申请号：US18349712

申请日：2023-07-10

申请人： SK hynix Inc.

发明人： Jae Yong SON ,  Dae Sung KIM ,  Min Su CHOI

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/14

CPC分类号： G06F11/1068 ,  G06F11/0772 ,  G06F11/141

摘要： A memory device may include a read controller and an error correction circuit. The read controller may sequentially perform a plurality of read retry operations on a memory device. The error correction circuit may perform a plurality of first error correction decodings on read data respectively acquired from the plurality of read retry operations, store a plurality of Unsatisfied Syndrome Check (USC) values respectively produced by the plurality of first error correction decodings, and perform a second error correction decoding based on read data corresponding to a minimum USC value among the plurality of USC values.

公开(公告)号：US20240029787A1

公开(公告)日：2024-01-25

申请号：US18063007

申请日：2022-12-07

申请人： SK hynix Inc.

发明人： Jae Yong SON ,  Nam Kyeong KIM ,  Hoon CHO ,  Hyuk Min KWON ,  Dae Sung KIM ,  Jang Seob KIM ,  Sang Ho YUN

IPC分类号： G11C11/4096 ,  G11C11/408 ,  G11C11/4078

CPC分类号： G11C11/4096 ,  G11C11/4085 ,  G11C11/4078

摘要： A storage device includes a memory including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, and a controller configured to control the memory and perform a read retry operation for the memory using a read retry table. The memory includes a special block that stores a read retry table in which a plurality of read retry values are set for each of a plurality of first conditions and each of a plurality of second conditions corresponding to each of the plurality of first conditions.

公开(公告)号：US20240355405A1

公开(公告)日：2024-10-24

申请号：US18469562

申请日：2023-09-19

申请人： SK hynix Inc.

发明人： Jae Yong SON ,  Nam Kyeong KIM

IPC分类号： G11C29/12 ,  G11C29/18 ,  G11C29/42

CPC分类号： G11C29/1201 ,  G11C29/18 ,  G11C29/42 ,  G11C2029/1202

摘要： A read retry table (RRT) apparatus is coupled to a plurality of memory dies via a data path. The apparatus is configured to collect data from a plurality of memory cells coupled to a plurality of word lines in the plurality of memory dies via the data path; perform a first clustering on the plurality of word lines based on an error correction capability of error correction circuitry for collected data; perform a second clustering on an outlier of the first clustering; and generate or update an RRT based on values obtained from the first clustering and the second clustering.

公开(公告)号：US20240281321A1

公开(公告)日：2024-08-22

申请号：US18447326

申请日：2023-08-10

申请人： SK hynix Inc.

发明人： Jae Yong SON ,  Dae Sung KIM ,  Min Su CHOI

IPC分类号： G06F11/10

CPC分类号： G06F11/10

摘要： Provided herein may be a memory controller and a memory system including the same. The memory controller may include an error correction circuit configured to perform error correction decoding on data that is read by read retry operations, a buffer memory configured to store decoding history information including retry fail voltages used for a failure in the read retry operations and syndrome weights respectively corresponding to the retry fail voltages, and a processor configured to, when a number of times that the read retry operations fail reaches a threshold number of times, determine a voltage corresponding to a minimum syndrome weight determined based on a relationship between changes in the syndrome weights relative to magnitudes of the retry fail voltages, to be an optimally estimated read voltage, and provide data that is read using the optimally estimated read voltage to the error correction circuit.