公开(公告)号：US20210249065A1

公开(公告)日：2021-08-12

申请号：US16920224

申请日：2020-07-02

Applicant: SK hynix Inc.

Inventor： Geun Ho CHOI ,  Kyung Mook KIM ,  Woongrae KIM

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4096

Abstract: A semiconductor device includes an internal column control signal generation circuit, a bank address transfer circuit, and a first bank control circuit. The internal column control signal generation circuit generates a column control signal to output an internal column control signal. The bank address transfer circuit receives a bank address to generate an inverted bank address and outputs the bank address and the inverted bank address. The first bank control circuit generates a first bank active signal based on at least one of the bank address and the inverted bank address and latches the first bank active signal based on the internal column control signal to generate a first bank column control signal.

公开(公告)号：US20230290399A1

公开(公告)日：2023-09-14

申请号：US17871636

申请日：2022-07-22

Applicant: SK hynix Inc.

Inventor： Kyung Mook KIM

IPC: G11C11/406 ,  G11C11/4072

CPC classification number: G11C11/406 ,  G11C11/4072

Abstract: A semiconductor memory device includes a refresh counter generating a counting address that is sequentially increasing according to a refresh command; an active latch generating an active address corresponding to an input address according to an active command; and a refresh control circuit repeatedly performing a first refresh period and a second refresh period according to the refresh command, and controlling selective refresh of one or more word lines corresponding to the counting address selected based on one or more high bits of the active address during the first refresh period and controlling sequential refresh of the word lines corresponding to the counting address during the second refresh period.

公开(公告)号：US20210366535A1

公开(公告)日：2021-11-25

申请号：US17011496

申请日：2020-09-03

Applicant: SK hynix Inc.

Inventor： Kyung Mook KIM ,  Woongrae KIM ,  Geun Ho CHOI

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

公开(公告)号：US20210327493A1

公开(公告)日：2021-10-21

申请号：US16931192

申请日：2020-07-16

Applicant: SK hynix Inc.

Inventor： Kyung Mook KIM ,  Do Hong KIM ,  Woongrae KIM ,  Sang Il PARK ,  Sang Woo YOON ,  Jong Seok HAN

IPC: G11C11/406 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4072

Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.

公开(公告)号：US20220293168A1

公开(公告)日：2022-09-15

申请号：US17830091

申请日：2022-06-01

Applicant: SK hynix Inc.

Inventor： Kyung Mook KIM ,  Woongrae KIM ,  Geun Ho CHOI

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

公开(公告)号：US20210383858A1

公开(公告)日：2021-12-09

申请号：US17009329

申请日：2020-09-01

Applicant: SK hynix Inc.

Inventor： Kyung Mook KIM ,  Woongrae KIM ,  Sang Il PARK ,  Seung Hun LEE

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/408

Abstract: A device includes an operation control circuit and a drive control signal generation circuit. The operation control circuit generates an internal refresh signal that is activated to perform an active operation for a cell array, the cell array being coupled to a word line that is selected by a row address based on a refresh signal that is activated to perform a refresh operation. In addition, the operation control circuit generates a pre-refresh pulse based on the refresh signal and generates a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit generates a drive control signal to control a drive of an active voltage that is supplied to the word line that is selected by the row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.

公开(公告)号：US20210350839A1

公开(公告)日：2021-11-11

申请号：US17354815

申请日：2021-06-22

Applicant: SK hynix Inc.

Inventor： Woongrae KIM ,  Kyung Mook KIM ,  Seung Hun LEE ,  Da In IM

IPC: G11C7/22 ,  G11C8/12 ,  G11C8/18

Abstract: An electronic device includes a shifting circuit and a dock repeater. The shifting circuit is configured to generate a write shifting flag that is inactivated when a write signal for a write operation is activated. The clock repeater is configured to block generation of a read repeating dock that is used in a read operation when the write shifting flag is inactivated.