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公开(公告)号：US20200176035A1
公开(公告)日：2020-06-04
申请号：US16506648
申请日：2019-07-09
Applicant: SK hynix Inc.
Inventor： Woongrae KIM , Myung Kyun KWAK , Seung Hun LEE
Abstract: A semiconductor device includes an input/output (I/O) control signal generation circuit, a pipe circuit and an auto-pre-charge signal generation circuit. The I/O control signal generation circuit generates an input control signal, an output control signal and an internal output control signal. The pipe circuit latches an internal command/address signal based on the input control signal and outputs the latched internal command/address signal as a latch signal. The auto-pre-charge signal generation circuit generates an auto-pre-charge signal from the latch signal and the internal latch signal.
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公开(公告)号：US20200150710A1
公开(公告)日：2020-05-14
申请号：US16507516
申请日：2019-07-10
Applicant: SK hynix Inc.
Inventor： Woongrae KIM , Seung Hun LEE
IPC: G06F1/04 , H03K3/012 , G11C5/14 , G06F1/3203
Abstract: A power gating system includes a logic circuit region including at least one logic gate configured to receive a first gating clock signal. The power gating system also includes a power gating control circuit configured to generate the first gating clock signal which is controlled to start transition after stabilization of an internal power voltage according to a chip select signal, a command/address signal, and an external clock signal.
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公开(公告)号：US20190341087A1
公开(公告)日：2019-11-07
申请号：US16144298
申请日：2018-09-27
Applicant: SK hynix Inc.
Inventor： Seung Hun LEE , Won Kyung CHUNG
Abstract: A mode register control circuit may include a masking signal generation circuit and a storage control pulse generation circuit. The masking signal generation circuit may be configured to generate a masking signal from data. The storage control pulse generation circuit may be configured to generate a storage control pulse for controlling a mode register write operation, from a mode register write pulse in response to the masking signal.
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4.发明申请CIRCUITS FOR SETTING REFERENCE VOLTAGES AND SEMICONDUCTOR DEVICES INCLUDING THE SAME 有权用于设置参考电压的电路和包括其的半导体器件公开(公告)号：US20170075367A1
公开(公告)日：2017-03-16
申请号：US15041258
申请日：2016-02-11
Applicant: SK hynix Inc.
Inventor： Seung Hun LEE , Won Kyung CHUNG
Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.
Abstract translation: 提供了用于设定参考电压的电路。 电路包括参考电压信息存储单元和参考电压输入/输出（I / O）控制单元。 参考电压信息存储单元被配置为如果训练操作以第一设置模式开始，则根据存储在第一寄存器或第二寄存器中的信息来设置参考电压的电平。 参考电压I / O控制单元被配置为如果训练操作以第二设定模式开始，则根据第一数据或第二数据来设置参考电压的电平。
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公开(公告)号：US20200160896A1
公开(公告)日：2020-05-21
申请号：US16400680
申请日：2019-05-01
Applicant: SK hynix Inc.
Inventor： Myung Kyun KWAK , Woongrae KIM , Seung Hun LEE
Abstract: A semiconductor device includes a burst end signal generation circuit and an auto-pre-charge control circuit. The burst end signal generation circuit generates a write burst end signal based on a write flag and a latched burst mode signal in a first burst mode and generates the write burst end signal based on an internal write flag and an internal latched burst mode signal in a second burst mode. The auto-pre-charge control circuit performs an auto-pre-charge operation based on the write burst end signal.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190296887A1
公开(公告)日：2019-09-26
申请号：US16142960
申请日：2018-09-26
Applicant: SK hynix Inc.
Inventor： Seung Hun LEE , Sang Sic YOON , Soo Young JANG , Jin Youp CHA
Abstract: A semiconductor apparatus includes a transmission device and a receiving device. The transmission device generates an output signal from a transmission signal in synchronization with a clock signal. The receiving device generates a reception signal from the output signal in synchronization with the clock signal and a delayed clock signal generated by delaying the clock signal by a preset time, based on an operating speed of the semiconductor apparatus.
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公开(公告)号：US20190131980A1
公开(公告)日：2019-05-02
申请号：US16012453
申请日：2018-06-19
Applicant: SK hynix Inc.
Inventor： Seung Hun LEE , Sang Sic Yoon
Abstract: A semiconductor apparatus may include a synchronization circuit, and a phase detection circuit. The synchronization circuit may be configured to, based on an operation mode of the semiconductor apparatus, divide a first clock signal to generate first and second divided clock signals or divide a phase-locked clock signal to generate first and second divided clock signals. The phase detection circuit may be configured to use, based on the operation mode of the semiconductor apparatus, either the first and second clock signals created from dividing the first clock signal or the first and second clock signals created from dividing the phase-locked clock signal, to compare either the first divided clock signal or the second divided clock signal with a second clock signal to generate a phase detection signal.
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公开(公告)号：US20210383858A1
公开(公告)日：2021-12-09
申请号：US17009329
申请日：2020-09-01
Applicant: SK hynix Inc.
Inventor： Kyung Mook KIM , Woongrae KIM , Sang Il PARK , Seung Hun LEE
IPC: G11C11/406 , G11C11/4074 , G11C11/408
Abstract: A device includes an operation control circuit and a drive control signal generation circuit. The operation control circuit generates an internal refresh signal that is activated to perform an active operation for a cell array, the cell array being coupled to a word line that is selected by a row address based on a refresh signal that is activated to perform a refresh operation. In addition, the operation control circuit generates a pre-refresh pulse based on the refresh signal and generates a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit generates a drive control signal to control a drive of an active voltage that is supplied to the word line that is selected by the row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.
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9.发明申请公开(公告)号：US20210377483A1
公开(公告)日：2021-12-02
申请号：US16769830
申请日：2018-06-14
Applicant: SK hynix Inc.
Inventor： Chang Hyun KIM , Wan Jun ROH , Doo Bock LEE , Seung Hun LEE , Jae Jin LEE , Chun Seok JEONG
Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.
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公开(公告)号：US20210350839A1
公开(公告)日：2021-11-11
申请号：US17354815
申请日：2021-06-22
Applicant: SK hynix Inc.
Inventor： Woongrae KIM , Kyung Mook KIM , Seung Hun LEE , Da In IM
Abstract: An electronic device includes a shifting circuit and a dock repeater. The shifting circuit is configured to generate a write shifting flag that is inactivated when a write signal for a write operation is activated. The clock repeater is configured to block generation of a read repeating dock that is used in a read operation when the write shifting flag is inactivated.
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