公开(公告)号：US20230238040A1

公开(公告)日：2023-07-27

申请号：US17831969

申请日：2022-06-03

Applicant: SK hynix Inc.

Inventor： Seung Han RYU ,  In Bo SHIM ,  Hyeong Rak KIM ,  Hae Seong JEONG

IPC: G11C7/10

CPC classification number: G11C7/1087 ,  G11C7/1093 ,  G11C7/109

Abstract: A storage device includes a memory device including a plurality of memory dies; and a memory controller for addressing a memory die among the plurality of memory dies by using an address latch enable (ALE) signal and a command latch enable (CLE) signal, which are input during predetermined N cycles, where N is a natural number, and controlling the memory device such that the one memory die performs a memory operation. The memory controller may address the memory die by addressing a channel among a plurality of channels respectively connected to a plurality of package groups by using a chip enable (CE) signal.

公开(公告)号：US20240282375A1

公开(公告)日：2024-08-22

申请号：US18448164

申请日：2023-08-11

Applicant: SK hynix Inc.

Inventor： Seung Han RYU ,  Sung Geun KANG ,  Hyeong Rak KIM

IPC: G11C14/00 ,  G06F3/06

CPC classification number: G11C14/0018 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0658 ,  G06F3/0679

Abstract: According to the present technology, a storage device includes a nonvolatile storage area including a plurality of backup memory blocks each including a plurality of memory cells respectively connected to a plurality of word lines, and a controller configured to control the nonvolatile storage area to determine a target memory block in which data is to be stored among the plurality of backup memory blocks, determine a reference word line among the plurality of word lines coupled to the target memory block, and perform a pre-conditioning operation of programming dummy data to memory cells connected to at least one of remaining word lines except for the reference word line among the plurality of word lines coupled to the target memory block.

公开(公告)号：US20190339761A1

公开(公告)日：2019-11-07

申请号：US16142102

申请日：2018-09-26

Applicant: SK hynix Inc.

Inventor： Seung Han RYU

IPC: G06F1/30 ,  H02J7/34 ,  G11C16/30 ,  G06F1/28 ,  G05F1/10 ,  G01R19/165

Abstract: An electronic device may include a semiconductor memory device, a central processing device that controls an operation of the semiconductor memory device, and a power supply that supplies power to the semiconductor memory device and the central processing device, and the power supply may include a power controller that receives external power and generates an internal voltage and a charge voltage, an auxiliary power unit that is charged by the charge voltage in a normal mode and provides charged power when sudden power loss occurs, and a charge voltage conversion unit that supplies the auxiliary power unit with the charge voltage at a first level in the normal mode, and converts the first level of the charge voltage to a second level higher than the first level and supplies the charge voltage to the auxiliary power unit in a test mode.