公开(公告)号：US20240194233A1

公开(公告)日：2024-06-13

申请号：US18328781

申请日：2023-06-05

Applicant: SK hynix Inc.

Inventor： Sung Geun KANG ,  In Bo SHIM ,  Su Il JIN ,  Eun Kyu CHOI

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1093 ,  G11C7/1096

Abstract: A memory system includes a memory device and a memory controller for providing data to the memory device based on a clock signal. The memory device includes a first memory group; a second memory group; an internal clock generator for generating a first internal clock signal and a second internal clock signal, which respectively correspond to a first period and a second period of the clock signal; and a data distributor for providing the data respectively to the first memory group and the second memory group, based on the first internal clock signal and the second internal clock signal.

公开(公告)号：US20230176771A1

公开(公告)日：2023-06-08

申请号：US17736815

申请日：2022-05-04

Applicant: SK hynix Inc.

Inventor： Jae Woong JEONG ,  In Bo SHIM ,  Na Yeong KIM ,  Dal Gon KIM

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A storage device includes a memory controller and a plurality of memory devices. The plurality of memory devices comprise a first memory device coupled to the memory controller and an nth memory device coupled in series to the first memory device, where n is a natural number greater than 1. The memory controller is configured to transmit, to a first memory device, a signal that includes a target ID indicating a selected memory device from among the plurality of memory devices. Each memory device includes a plurality of memory dies, an interface configured to distribute the signal based on the target ID, and a redriver configured to redrive the signal such that the signal is transferred to another memory device.

公开(公告)号：US20230378787A1

公开(公告)日：2023-11-23

申请号：US18048819

申请日：2022-10-21

Applicant: SK hynix Inc.

Inventor： Su Il JIN ,  In Bo SHIM ,  Won Seob SONG ,  Jin Yeon WON

IPC: H02J7/00

CPC classification number: H02J7/005 ,  H02J7/007182 ,  H02J7/00032 ,  H02J2207/50

Abstract: A power supply apparatus may include a charging circuit configured to receive an external voltage and to generate a charging voltage by charging and discharging energy by switching according to a level of the charging voltage; an auxiliary power circuit configured to store an electric charge using the charging voltage; and a health monitoring circuit configured to determine a charging health state of the auxiliary power circuit by counting a number of switchings of the charging circuit during an interval in which the charging voltage rises to a first level from a second level, the determined charging health state being based on the number of switchings.

公开(公告)号：US20220209573A1

公开(公告)日：2022-06-30

申请号：US17348549

申请日：2021-06-15

Applicant: SK hynix Inc.

Inventor： Eun Kyu CHOI ,  Seon Cheol KIM ,  Sung Ryun MOON ,  In Bo SHIM ,  Joon Hwan OH

IPC: H02J9/06 ,  G11C5/14

Abstract: Auxiliary power management devices are disclosed. In some implementations, an auxiliary power management device may be coupled to an auxiliary power source that serves as a backup power supply for a primary power source to provide power to an electronic device and comprising a plurality of switches to control currents of a plurality of energy storage components, a plurality of channels coupled to the plurality of switches, respectively, a plurality of switch controllers to control the plurality of switches coupled to the plurality of channels and monitor a current or voltage of the plurality of channels, and a management logic to control the switches coupled to the plurality of channels upon detection, by the plurality of switch controllers, of a first current or voltage distribution across the channels that exceeds a predetermined threshold regarding the current or voltage distribution.

公开(公告)号：US20230238040A1

公开(公告)日：2023-07-27

申请号：US17831969

申请日：2022-06-03

Applicant: SK hynix Inc.

Inventor： Seung Han RYU ,  In Bo SHIM ,  Hyeong Rak KIM ,  Hae Seong JEONG

IPC: G11C7/10

CPC classification number: G11C7/1087 ,  G11C7/1093 ,  G11C7/109

Abstract: A storage device includes a memory device including a plurality of memory dies; and a memory controller for addressing a memory die among the plurality of memory dies by using an address latch enable (ALE) signal and a command latch enable (CLE) signal, which are input during predetermined N cycles, where N is a natural number, and controlling the memory device such that the one memory die performs a memory operation. The memory controller may address the memory die by addressing a channel among a plurality of channels respectively connected to a plurality of package groups by using a chip enable (CE) signal.