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Patent Agency Ranking
公开(公告)号：US09225316B2
公开(公告)日：2015-12-29
申请号：US14668488
申请日：2015-03-25
Applicant: SK hynix Inc.
Inventor： Shin-Deok Kang , Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
CPC classification number: H03K3/017 , H03K5/1565
Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
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公开(公告)号：US10079606B2
公开(公告)日：2018-09-18
申请号：US14793451
申请日：2015-07-07
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Dae-Han Kwon , Shin-Deok Kang
CPC classification number: H03K23/662 , G06F1/04
Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.
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公开(公告)号：US09257968B2
公开(公告)日：2016-02-09
申请号：US14668542
申请日：2015-03-25
Applicant: SK hynix Inc.
Inventor： Shin-Deok Kang , Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
CPC classification number: H03K3/017 , H03K5/1565
Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
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公开(公告)号：US10256823B2
公开(公告)日：2019-04-09
申请号：US16106658
申请日：2018-08-21
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Dae-Han Kwon , Shin-Deok Kang
Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.
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公开(公告)号：US09018994B2
公开(公告)日：2015-04-28
申请号：US13844928
申请日：2013-03-16
Applicant: SK Hynix Inc.
Inventor： Shin-Deok Kang , Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
CPC classification number: H03K3/017 , H03K5/1565
Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
Abstract translation: 占空比校正电路包括：时钟调整单元，被配置为响应于占空比控制信号调整输入时钟信号的占空比并产生输出时钟信号;跟踪类型设置单元，被配置为产生用于设置的跟踪类型选择信号 基于输出时钟信号的占空比锁定状态的第一或第二跟踪类型，以及控制信号生成单元，被配置为响应于跟踪类型选择生成并入第一或第二跟踪类型的占空比控制信号 信号和输出时钟信号。
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