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公开(公告)号：US09018994B2
公开(公告)日：2015-04-28
申请号：US13844928
申请日：2013-03-16
Applicant: SK Hynix Inc.
Inventor： Shin-Deok Kang , Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
CPC classification number: H03K3/017 , H03K5/1565
Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
Abstract translation: 占空比校正电路包括：时钟调整单元，被配置为响应于占空比控制信号调整输入时钟信号的占空比并产生输出时钟信号;跟踪类型设置单元，被配置为产生用于设置的跟踪类型选择信号 基于输出时钟信号的占空比锁定状态的第一或第二跟踪类型，以及控制信号生成单元，被配置为响应于跟踪类型选择生成并入第一或第二跟踪类型的占空比控制信号 信号和输出时钟信号。
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公开(公告)号：US09128511B2
公开(公告)日：2015-09-08
申请号：US13709991
申请日：2012-12-10
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Dae-Han Kwon , Jae-Min Jang
IPC: G06F3/00 , G11C7/22 , G11C7/10 , G11C11/4076 , G11C11/4093 , G11C11/4096
CPC classification number: G06F3/00 , G11C7/1012 , G11C7/1066 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096
Abstract: A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.
Abstract translation: 半导体器件包括：特征码存储单元，被配置为存储通过给定焊盘输入的信号传送特性信息，并输出与信号传送特性信息相对应的控制代码;以及特性反射单元，被配置为将信号传送特性信息反映在输入 响应于控制代码通过给定焊盘的信号输入，并输出反射的输入信号。
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公开(公告)号：US09361969B2
公开(公告)日：2016-06-07
申请号：US14278031
申请日：2014-05-15
Applicant: SK hynix Inc.
Inventor： Yong-Ju Kim , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
IPC: G11C7/04 , G11C11/406
CPC classification number: G11C11/40626
Abstract: A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal.
Abstract translation: 一种半导体器件包括周期性信号发生电路，用于响应于作为默认值的第一微调信号产生具有设定周期而不管温度变化的周期信号，并且响应于该温度控制周期信号的设定周期 第二微调信号和内部电路，以响应周期信号执行设定操作。
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Patent Agency Ranking
公开(公告)号：US09257968B2
公开(公告)日：2016-02-09
申请号：US14668542
申请日：2015-03-25
Applicant: SK hynix Inc.
Inventor： Shin-Deok Kang , Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
CPC classification number: H03K3/017 , H03K5/1565
Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
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公开(公告)号：US08686768B2
公开(公告)日：2014-04-01
申请号：US13844865
申请日：2013-03-16
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Jae-Min Jang
IPC: H03L7/06
Abstract: A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.
Abstract translation: 锁相环包括相位检测器，被配置为将输入时钟的相位与反馈时钟的相位进行比较以产生相位比较结果，初始频率值提供器被配置为检测输入时钟的频率并提供频率检测 结果，配置为基于相位比较结果和频率检测结果产生频率控制信号的控制器，以及响应于频率控制信号产生输出时钟的振荡器。
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公开(公告)号：US20130076401A1
公开(公告)日：2013-03-28
申请号：US13680239
申请日：2012-11-19
Applicant: SK HYNIX INC.
Inventor： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC: H03K5/153
CPC classification number: H03K5/153
Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。
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公开(公告)号：US09225316B2
公开(公告)日：2015-12-29
申请号：US14668488
申请日：2015-03-25
Applicant: SK hynix Inc.
Inventor： Shin-Deok Kang , Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
CPC classification number: H03K3/017 , H03K5/1565
Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
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公开(公告)号：US08461878B2
公开(公告)日：2013-06-11
申请号：US13680239
申请日：2012-11-19
Applicant: SK Hynix Inc.
Inventor： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC: H03K5/153
CPC classification number: H03K5/153
Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。
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