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公开(公告)号：US20180322940A1
公开(公告)日：2018-11-08
申请号：US15832205
申请日：2017-12-05
Applicant: SK hynix Inc.
Inventor： Yong-Ju Kim , Dong-Gun Kim , Do-Sun Hong
CPC classification number: G11C29/52 , G06F3/0659 , G06F11/1068 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2211/4062
Abstract: A method for operating a memory system includes: reading a data from a memory device; detecting and correcting an error of the data; when the error of the data is equal to or greater than a threshold value, deciding an address corresponding to memory cells from which the data is read in the memory device as a rewrite-requiring address; and rewriting the data of the memory cell corresponding to the rewrite-requiring address.
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公开(公告)号：US10079606B2
公开(公告)日：2018-09-18
申请号：US14793451
申请日：2015-07-07
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Dae-Han Kwon , Shin-Deok Kang
CPC classification number: H03K23/662 , G06F1/04
Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.
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公开(公告)号：US09787296B1
公开(公告)日：2017-10-10
申请号：US15234954
申请日：2016-08-11
Applicant: SK hynix Inc.
Inventor： Sung-Eun Lee , Kyung-Hoon Kim , Myeong-Jae Park , Woo-Yeol Shin , Han-Kyu Chi , Yong-Ju Kim
CPC classification number: H03K5/159 , H03K5/131 , H03K21/38 , H03K2005/00078 , H03K2005/00247 , H03K2005/00273
Abstract: A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.
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公开(公告)号：US09361969B2
公开(公告)日：2016-06-07
申请号：US14278031
申请日：2014-05-15
Applicant: SK hynix Inc.
Inventor： Yong-Ju Kim , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
IPC: G11C7/04 , G11C11/406
CPC classification number: G11C11/40626
Abstract: A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal.
Abstract translation: 一种半导体器件包括周期性信号发生电路，用于响应于作为默认值的第一微调信号产生具有设定周期而不管温度变化的周期信号，并且响应于该温度控制周期信号的设定周期 第二微调信号和内部电路，以响应周期信号执行设定操作。
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公开(公告)号：US09257968B2
公开(公告)日：2016-02-09
申请号：US14668542
申请日：2015-03-25
Applicant: SK hynix Inc.
Inventor： Shin-Deok Kang , Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
CPC classification number: H03K3/017 , H03K5/1565
Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
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Patent Agency Ranking
公开(公告)号：US10795763B2
公开(公告)日：2020-10-06
申请号：US16203862
申请日：2018-11-29
Applicant: SK hynix Inc.
Inventor： Yong-Ju Kim , Do-Sun Hong , Dong-Gun Kim
Abstract: A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.
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公开(公告)号：US10394465B2
公开(公告)日：2019-08-27
申请号：US15089195
申请日：2016-04-01
Applicant: SK hynix Inc.
Inventor： Young-Ook Song , Yong-Kee Kwon , Yong-Ju Kim
Abstract: A semiconductor device includes: a first memory chip including a plurality of first memory regions; a temporary memory chip including a plurality of temporary memory regions; and a control chip suitable for accessing a first access target memory region among the plurality of first memory regions or a first temporary memory region among the plurality of temporary memory regions based on first access information and first temperature readout information corresponding to the plurality of first memory regions.
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公开(公告)号：US10140025B2
公开(公告)日：2018-11-27
申请号：US15270755
申请日：2016-09-20
Applicant: SK hynix Inc.
Inventor： Hyung-Gyun Yang , Yong-Ju Kim , Hong-Sik Kim
Abstract: A memory system may include a memory device suitable for storing data requested from a host, and a controller suitable for generating information on the data and transmitting/receiving the data and the information to/from the memory device through first and second data buses, respectively, during a first operation mode, or for transmitting/receiving the data to/from the memory device through one of the first and second data buses based on the data size, during a second operation mode.
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公开(公告)号：US20180240516A1
公开(公告)日：2018-08-23
申请号：US15831979
申请日：2017-12-05
Applicant: SK hynix Inc.
Inventor： Sang-Gu Jo , Jung-Hyun Kwon , Sung-Eun Lee , Yong-Ju Kim
CPC classification number: G11C11/5642 , G06F3/0679 , G06F13/1626 , G11C7/22 , G11C13/0004 , G11C13/004 , G11C16/0483 , G11C16/26 , G11C16/3404 , G11C2013/005 , G11C2207/2245 , G11C2207/2254
Abstract: A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.
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公开(公告)号：US09990312B2
公开(公告)日：2018-06-05
申请号：US15257389
申请日：2016-09-06
Applicant: SK hynix Inc.
Inventor： Sung-Eun Lee , Jung-Hyun Kwon , Jing-Zhe Xu , Yong-Ju Kim
CPC classification number: G06F13/161 , G06F13/1684 , G06F13/4027 , G06F13/404 , G11C29/76 , G11C29/88
Abstract: A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.
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