公开(公告)号：US12095465B2

公开(公告)日：2024-09-17

申请号：US17899030

申请日：2022-08-30

Applicant: SK hynix Inc.

Inventor： Sun Ki Cho ,  Yang Ho Sur ,  Ic Su Oh

IPC: H03K5/01 ,  H03K5/00

CPC classification number: H03K5/01 ,  H03K2005/00078

Abstract: An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.

公开(公告)号：US20220069813A1

公开(公告)日：2022-03-03

申请号：US17171719

申请日：2021-02-09

Applicant: SK hynix Inc.

Inventor： Sun Ki Cho ,  Dong Uc Ko ,  Yang Ho Sur ,  Jun Yong Song ,  Sung Gil Jang ,  Hae Kang Jung ,  Min Sung Cheon ,  Chang Kyu Choi ,  Tae Jin Hwang

IPC: H03K5/02 ,  H03F3/45

Abstract: A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.

公开(公告)号：US11271553B1

公开(公告)日：2022-03-08

申请号：US17171719

申请日：2021-02-09

Applicant: SK hynix Inc.

Inventor： Sun Ki Cho ,  Dong Uc Ko ,  Yang Ho Sur ,  Jun Yong Song ,  Sung Gil Jang ,  Hae Kang Jung ,  Min Sung Cheon ,  Chang Kyu Choi ,  Tae Jin Hwang

IPC: H03K5/00 ,  H03K5/02 ,  H03F3/45

Abstract: A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.