Abstract:
An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.
Abstract:
A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
Abstract:
Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.
Abstract:
A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
Abstract:
A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
Abstract:
A semiconductor device is disclosed, which relates to a technology for reducing current consumption of a semiconductor chip configured to operate a transmitter (Tx) at a high speed. The semiconductor device includes a data driving unit configured to output a pull-up drive signal and a pull-down drive signal by level-shifting an input signal according to a clock signal; and a data output unit configured to adjust slew rates of the pull-up drive signal and the pull-down drive signal according to a code signal, and output impedance-adjusted signals to an output terminal.
Abstract:
Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.