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公开(公告)号：US20230096254A1
公开(公告)日：2023-03-30
申请号：US17955034
申请日：2022-09-28
摘要： In some embodiments, a calibration circuit can include a first circuit configured to generate a first output voltage based on a first reference voltage, and a second circuit configured to compare the first output voltage and a second reference voltage. The calibration circuit can further include a calibration block configured to provide an adjustment to the first circuit based on the comparison of the first output voltage and the second reference voltage, with the adjustment being configured to compensate for a change in the first reference voltage. In some embodiments, such a calibration circuit can be utilized for and/or be a part of a digital-to-analog converter for wireless audio applications.
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公开(公告)号：US20230100998A1
公开(公告)日：2023-03-30
申请号：US17955244
申请日：2022-09-28
发明人： Rie SASAKAWA , Wai Laing LEE
摘要： A startup circuit for a bandgap reference source can include a first transistor coupled to a supply source and configured to provide a current to a reference resistance when the bandgap reference source is turned on, to thereby provide a reference voltage at a first node between the first transistor and the reference resistance, a second transistor coupled to the supply source to provide a second node therebetween, the second transistor having a gate coupled to the first node, such that the second transistor is off and a startup voltage at the second node is up when the reference voltage is at or below a threshold voltage, and the second transistor is on and the startup voltage at the second node is down when the reference voltage exceeds the threshold voltage, and a third transistor implemented between the supply source and a startup node of a bandgap core, the third transistor having a gate coupled to the second node such that the third transistor turns on to inject a startup current to the startup node when the startup voltage is up, and turns off when the startup voltage is down.
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公开(公告)号：US20230283291A1
公开(公告)日：2023-09-07
申请号：US18117375
申请日：2023-03-03
发明人： Min Gyu KIM , Joseph HAMILTON , Timir NANDI , Barkat A. WANI , Praveen Kumar VENKATACHALA , Wai Laing LEE , Michael Jon WURTZ , Humberto CAMPANELLA-PINEDA
IPC分类号： H03M3/00
CPC分类号： H03M3/464 , H04R2201/003 , H04R1/08
摘要： In some embodiments, an analog-to-digital converter (ADC) architecture can be implemented to process a signal from a charge output sensor. The ADC architecture can include a summing node for receiving a sensor signal from the charge output sensor, and an output node implemented to provide a digital signal representative of the sensor signal. The ADC architecture can further include a charge amplifier implemented to receive an analog signal from the summing node as an input analog signal and generate an output analog signal with a gain, and an ADC circuit implemented to generate the digital signal based on the output analog signal from the charge amplifier. The ADC architecture can further include a feedback circuit implemented between the output node and the summing node.
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公开(公告)号：US20230103164A1
公开(公告)日：2023-03-30
申请号：US17955000
申请日：2022-09-28
发明人： Spencer David LEUENBERGER , Deepika KUMARI , David LAMB , Mark R. PETING , Evan Michael ALBRIGHT , Wai Laing LEE , Amit KUMAR
摘要： In some embodiments, a calibration circuit for an audio amplification system can include a tone generator configured to provide a tone having a frequency to an input path of an audio amplifier, such that an input signal provided to the audio amplifier includes the tone, a a first sampling circuit configured to sample an output signal at an output node of the audio amplifier, and a second sampling circuit configured to sample the input signal at an input node of the audio amplifier. The calibration circuit can further include a gain adjustment circuit configured to generate a correction signal based on the sampled output signal and the sampled input signal to correct for a gain variation of the audio amplifier.
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公开(公告)号：US20230102120A1
公开(公告)日：2023-03-30
申请号：US17955292
申请日：2022-09-28
摘要： In some embodiments, a digital-to-analog converter (DAC) architecture can include an array having a total number of bit cells, and a control system configured to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells. The selected number can be variable, such that the array consumes a quiescent current that depends on the selected number. The control system can be further configured to change the selected number when a signal condition exceeds a threshold duration.
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公开(公告)号：US20230098492A1
公开(公告)日：2023-03-30
申请号：US17955219
申请日：2022-09-28
IPC分类号： H03F3/217
摘要： In some embodiments, an audio amplifier can include an input for receiving a signal to be amplified, and an amplification stage configured to amplify the signal based on pulse width modulation and provide the amplified signal at an output node. The audio amplifier can further include a feedback circuit implemented between the output node and the input node. The feedback circuit can include a series arrangement of a high bandwidth input common mode loop and a low bandwidth output common mode loop, with the low bandwidth output common mode loop configured to provide a desired phase change for the high bandwidth input common mode loop.
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