公开(公告)号：US11908799B2

公开(公告)日：2024-02-20

申请号：US17322570

申请日：2021-05-17

Applicant: SOCIONEXT INC.

Inventor： Hideyuki Komuro ,  Junji Iwahori

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L27/092

Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.

公开(公告)号：US12191345B2

公开(公告)日：2025-01-07

申请号：US18598870

申请日：2024-03-07

Applicant: Socionext Inc.

Inventor： Isaya Sobue ,  Hideyuki Komuro

IPC: H01L21/00 ,  H01L27/06 ,  H01L49/02 ,  H01L23/528 ,  H01L27/092

Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.

公开(公告)号：US12094882B2

公开(公告)日：2024-09-17

申请号：US17719052

申请日：2022-04-12

Applicant: Socionext Inc.

Inventor： Hideyuki Komuro ,  Toshio Hino ,  Tomoya Tsuruta

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11881

Abstract: In a power line structure for supplying power to standard cells, buried power lines extending in the X direction are placed at a given spacing in the Y direction. A local power line extending in the Y direction is connected with the buried power lines. Metal power lines extending in the X direction are formed in an upper-layer metal interconnect layer and connected with the local power line. The spacing of placement of the metal power lines in the Y direction is greater than the spacing of placement of the buried power lines.

公开(公告)号：US12255141B2

公开(公告)日：2025-03-18

申请号：US18410874

申请日：2024-01-11

Applicant: SOCIONEXT INC.

Inventor： Hideyuki Komuro ,  Junji Iwahori

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092

Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.

公开(公告)号：US12119349B2

公开(公告)日：2024-10-15

申请号：US17404639

申请日：2021-08-17

Applicant: SOCIONEXT INC.

Inventor： Hideyuki Komuro ,  Tomoya Tsuruta ,  Yasuhiro Nakaoka

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/118

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11807

Abstract: A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.

公开(公告)号：US11955508B2

公开(公告)日：2024-04-09

申请号：US17546463

申请日：2021-12-09

Applicant: Socionext Inc.

Inventor： Isaya Sobue ,  Hideyuki Komuro

IPC: H01L21/00 ,  H01L27/06 ,  H01L49/02 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L23/5286 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.