公开(公告)号：US09812441B2

公开(公告)日：2017-11-07

申请号：US15402952

申请日：2017-01-10

Applicant: SOCIONEXT INC.

Inventor： Koichi Taniguchi ,  Masato Maede

IPC: H01L27/02 ,  H01L23/50 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/0292 ,  H01L23/50 ,  H01L23/528 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0928 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2924/0002 ,  H03K3/354 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.

公开(公告)号：US09379101B2

公开(公告)日：2016-06-28

申请号：US14684323

申请日：2015-04-10

Applicant: SOCIONEXT INC.

Inventor： Koichi Taniguchi ,  Masato Maede

IPC: H01L27/02 ,  H01L23/544 ,  H01L27/092

CPC classification number: H01L27/0292 ,  H01L23/50 ,  H01L23/528 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0928 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2924/0002 ,  H03K3/354 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.

公开(公告)号：US09576947B2

公开(公告)日：2017-02-21

申请号：US15147555

申请日：2016-05-05

Applicant: Socionext Inc.

Inventor： Koichi Taniguchi ,  Masato Maede

IPC: H01L27/02 ,  H01L23/50 ,  H01L23/528 ,  H01L29/06 ,  H03K3/354 ,  H01L27/092 ,  H01L23/544

CPC classification number: H01L27/0292 ,  H01L23/50 ,  H01L23/528 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0928 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2924/0002 ,  H03K3/354 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.

Abstract translation: 在半导体集成电路器件中，用于外部连接的多个电极焊盘被布置成Z字形图案。 多个I / O单元的靠近半导体芯片的一侧的电极焊盘的一些电极焊盘各自具有靠近半导体芯片侧的端部，其端部设置在与半导体芯片的相同位置 对应的I / O单元的端部。 电源侧保护电路靠近刻划区域设置有电源侧保护电路和防止静电放电的接地侧保护电路。 一个电极焊盘的中心位置与相应的I / O单元的接地侧保护电路之间的距离以及另一个电极焊盘的中心位置与相应的I电极的接地侧保护电路之间的距离 / O单元都是短的，并且在每个I / O单元之间基本相等。

公开(公告)号：US10366980B2

公开(公告)日：2019-07-30

申请号：US15722901

申请日：2017-10-02

Applicant: SOCIONEXT INC.

Inventor： Koichi Taniguchi ,  Masato Maede

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L23/544 ,  H01L23/50 ,  H01L23/528 ,  H03K3/354

Abstract: A semiconductor chip including an internal circuit, a plurality of electrode pads and a plurality of I/O cells. The plurality of electrode pads are arranged on a first line, a second line and a third line. Each of the plurality of electrode pads arranged at least on the first and second lines overlaps corresponding one of the plurality of I/O cells in a plan view. The plurality of I/O cells are provided on a peripheral region of the semiconductor chip. Each of the plurality of I/O cells includes a protective circuit, and is connected to corresponding one of the plurality of electrode pads. The protective circuit includes a power source-side protective circuit provided between the corresponding one of the plurality of electrode pads and a power source wiring; and a ground-side protective circuit provided between the corresponding one of the plurality of electrode pads and a ground wiring.

公开(公告)号：US10692856B2

公开(公告)日：2020-06-23

申请号：US16441361

申请日：2019-06-14

Applicant: SOCIONEXT INC.

Inventor： Koichi Taniguchi ,  Masato Maede

IPC: H01L27/02 ,  H01L29/06 ,  H03K3/354 ,  H01L27/092 ,  H01L23/544 ,  H01L23/50 ,  H01L23/528

Abstract: A semiconductor chip including an internal circuit, a plurality of electrode pads and a plurality of I/O cells. The plurality of electrode pads are arranged on a first line, a second line and a third line. Each of the plurality of electrode pads arranged at least on the first and second lines overlaps corresponding one of the plurality of I/O cells in a plan view. The plurality of I/O cells are provided on a peripheral region of the semiconductor chip. Each of the plurality of I/O cells includes a protective circuit, and is connected to corresponding one of the plurality of electrode pads. The protective circuit includes a power source-side protective circuit provided between the corresponding one of the plurality of electrode pads and a power source wiring; and a ground-side protective circuit provided between the corresponding one of the plurality of electrode pads and a ground wiring.