公开(公告)号：US20230185250A1

公开(公告)日：2023-06-15

申请号：US17998519

申请日：2021-06-02

Applicant: SOCPRA SCIENCES ET GENIE S.E.C.

Inventor： Frédéric NOLET ,  Nicolas ROY ,  Jean-François PRATTE ,  Frederik DUBOIS

IPC: G04F10/00 ,  H03K3/03 ,  H03K5/01

CPC classification number: G04F10/005 ,  H03K3/0315 ,  H03K5/01 ,  H03K2005/00078

Abstract: Time-to-digital converter (TDC) using multiple Vernier in a cascaded architecture reduces the timing jitter by decreasing the number of the ring oscillator cycles during the measurement processes. Time-to-digital converter (TDC) measurements using a third oscillator for the second Vernier process has significant advantages compared to changing the period of the second oscillator during the measurement cycle. The Vernier architecture described herein may operate with faster oscillators, reducing the number of intervals before converging and leading to a lower time conversion and a better timing jitter Adding multiple cascaded Vernier interpolation may further improve the TDC measurement resolution while having only a small increment of time required to resolve the time interval calculations.

公开(公告)号：US20240113147A1

公开(公告)日：2024-04-04

申请号：US18526681

申请日：2023-12-01

Applicant: SOCPRA SCIENCES ET GENIE S.E.C.

Inventor： Jean-François PRATTE ,  Samuel PARENT ,  Serge CHARLEBOIS ,  Henri DAUTET

IPC: H01L27/146 ,  H01L31/107

CPC classification number: H01L27/14636 ,  H01L27/1463 ,  H01L31/107

Abstract: This disclosure pertains to a new thinned down frontside illuminated 3D SiPM architecture, e.g. a Photon-to-Digital Converter, with direct interconnect layers between the SPAD and the CMOS. The described architecture removes the need to have through-silicon-vias. Additionally, this new architecture also provides low jitter operation of the SPADs. The architecture described herein, with extended isolation trenches through the entire thickness of the thinned down SPAD substrate, enables both the SPAD cell to be electrically and optically isolated from the other SPAD cells. As such, the crosstalk is minimized and direct backside connection is possible.

公开(公告)号：US20240152097A1

公开(公告)日：2024-05-09

申请号：US18482082

申请日：2023-10-06

Applicant: SOCPRA SCIENCES ET GENIE S.E.C.

Inventor： Frédéric NOLET ,  Nicolas ROY ,  Jean-François PRATTE ,  Frederik DUBOIS

IPC: G04F10/00 ,  H03K3/03 ,  H03K5/01

CPC classification number: G04F10/005 ,  H03K3/0315 ,  H03K5/01 ,  H03K2005/00078

Abstract: Time-to-digital converter (TDC) using multiple Vernier in a cascaded architecture reduces the timing jitter by decreasing the number of the ring oscillator cycles during the measurement processes. Time-to-digital converter (TDC) measurements using a third oscillator for the second Vernier process has significant advantages compared to changing the period of the second oscillator during the measurement cycle. The Vernier architecture described herein may operate with faster oscillators, reducing the number of intervals before converging and leading to a lower time conversion and a better timing jitter. Adding multiple cascaded Vernier interpolation may further improve the TDC measurement resolution while having only a small increment of time required to resolve the time interval calculations.