公开(公告)号：US10979058B2

公开(公告)日：2021-04-13

申请号：US16097658

申请日：2017-04-27

Applicant: SONY CORPORATION

Inventor： Makoto Masuda ,  Hiroaki Fujita ,  Tetsuya Fujiwara

IPC: H03L7/085 ,  G01R31/317 ,  H03K3/037 ,  H03K19/20 ,  H03K21/08

Abstract: The present technology relates to a first edge detector that detects whether there is an edge of a second clock signal in one cycle of a first clock signal. A second edge detector detects whether there is an edge of the first clock signal in one cycle of the second clock signal. The logic circuit performs a logical operation on a detection result from the first edge detector and a detection result from the second edge detector. The present technology can be applied to a circuit or the like that detects a locked state of a PLL circuit, for example.