公开(公告)号：US10819440B2

公开(公告)日：2020-10-27

申请号：US16703149

申请日：2019-12-04

Applicant: Sony Corporation

Inventor： Hiroaki Fujita ,  Hiroaki Nakano ,  Uichiro Omae ,  Tetsuya Fujiwara

IPC: H04B10/556 ,  H04B5/00 ,  H04W52/08 ,  H04W52/10 ,  H04W52/42 ,  H04W88/02

Abstract: A communication device of the disclosure includes a phase synchronizer, a modulator, and a controller. The phase synchronizer generates a second signal on a basis of a first signal received from a communication partner by selectively performing one of a closed loop operation and an open loop operation. The modulator is able to modulate the first signal on a basis of the second signal. The controller controls operations of the phase synchronizer and the modulator.

公开(公告)号：US09281826B2

公开(公告)日：2016-03-08

申请号：US14626109

申请日：2015-02-19

Applicant: Sony Corporation

Inventor： Tetsuya Fujiwara ,  Yusuke Tanaka ,  Norihito Suzuki

IPC: H03B5/12 ,  H03L7/06

CPC classification number: H03L7/06 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/005 ,  H03B2201/011 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03J2200/10

Abstract: A circuit includes first and second capacitances arranged on a first path that connects first and second terminals; a first switch arranged between the first capacitance and the second capacitance; a second switch arranged on a second path that connects a reference voltage section and a first node formed between the first capacitance and the first switch; a third switch arranged on a third path that connects the section and a second node formed between the second capacitance and the first switch; a first resistance arranged on a fourth path that connects the first node and a third node formed between the first terminal and the first capacitance; a second resistance arranged on a fifth path that connects the second node and a fourth node formed between the second terminal and the second capacitance; a fourth switch on the fourth path; and a fifth switch on the fifth path.

Abstract translation: 电路包括布置在连接第一和第二端子的第一路径上的第一和第二电容; 布置在所述第一电容和所述第二电容之间的第一开关; 布置在连接参考电压部分和形成在第一电容和第一开关之间的第一节点的第二路径上的第二开关; 布置在连接所述部分的第三路径上的第三开关和形成在所述第二电容和所述第一开关之间的第二节点; 布置在连接所述第一节点和形成在所述第一端子和所述第一电容之间的第三节点的第四路径上的第一电阻; 布置在连接所述第二节点的第五路径上的第二电阻和形成在所述第二端子和所述第二电容之间的第四节点; 第四路上的第四个开关; 和第五路上的第五个开关。

公开(公告)号：US20150256185A1

公开(公告)日：2015-09-10

申请号：US14626109

申请日：2015-02-19

Applicant: SONY CORPORATION

Inventor： Tetsuya Fujiwara ,  Yusuke Tanaka ,  Norihito Suzuki

IPC: H03L7/06 ,  H03K3/36

CPC classification number: H03L7/06 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/005 ,  H03B2201/011 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03J2200/10

Abstract: A circuit includes first and second capacitances arranged on a first path that connects first and second terminals; a first switch arranged between the first capacitance and the second capacitance; a second switch arranged on a second path that connects a reference voltage section and a first node formed between the first capacitance and the first switch; a third switch arranged on a third path that connects the section and a second node formed between the second capacitance and the first switch; a first resistance arranged on a fourth path that connects the first node and a third node formed between the first terminal and the first capacitance; a second resistance arranged on a fifth path that connects the second node and a fourth node formed between the second terminal and the second capacitance; a fourth switch on the fourth path; and a fifth switch on the fifth path.

Abstract translation: 电路包括布置在连接第一和第二端子的第一路径上的第一和第二电容; 布置在所述第一电容和所述第二电容之间的第一开关; 布置在连接参考电压部分和形成在第一电容和第一开关之间的第一节点的第二路径上的第二开关; 布置在连接所述部分的第三路径上的第三开关和形成在所述第二电容和所述第一开关之间的第二节点; 布置在连接所述第一节点和形成在所述第一端子和所述第一电容之间的第三节点的第四路径上的第一电阻; 布置在连接所述第二节点的第五路径上的第二电阻和形成在所述第二端子和所述第二电容之间的第四节点; 第四路上的第四个开关; 和第五路上的第五个开关。

公开(公告)号：US20140286470A1

公开(公告)日：2014-09-25

申请号：US14208077

申请日：2014-03-13

Applicant: Sony Corporation

Inventor： Zhiwei Zhou ,  Takashi Masuda ,  Tetsuya Fujiwara

IPC: H03L7/099 ,  H03L7/093

CPC classification number: H03L7/087 ,  H03L7/095 ,  H03L7/0995

Abstract: A clock and data recovery circuit includes: a first current source configured to supply a charge current through a first signal line; a second current source configured to supply a discharge current through a second signal line; a loop filter configured to convert the charge current into a first voltage signal and output the first voltage signal through a third signal line, and to convert the discharge current into a second voltage signal and output the second voltage signal through a fourth signal line; a voltage control oscillator configured to be controlled in frequency; and a phase detector configured to receive a data signal from outside and receive a clock signal from the voltage control oscillator, and to supply a control signal to each of the first current source and the second current source, and generate a recovery clock signal and a recovery data signal.

Abstract translation: 时钟和数据恢复电路包括：被配置为通过第一信号线提供充电电流的第一电流源; 第二电流源，被配置为通过第二信号线提供放电电流; 环路滤波器，被配置为将充电电流转换成第一电压信号，并通过第三信号线输出第一电压信号，并将放电电流转换成第二电压信号，并通过第四信号线输出第二电压信号; 配置为频率控制的电压控制振荡器; 以及相位检测器，被配置为从外部接收数据信号并从压控振荡器接收时钟信号，并且向第一电流源和第二电流源中的每一个提供控制信号，并产生恢复时钟信号和 恢复数据信号。

公开(公告)号：US10979058B2

公开(公告)日：2021-04-13

申请号：US16097658

申请日：2017-04-27

Applicant: SONY CORPORATION

Inventor： Makoto Masuda ,  Hiroaki Fujita ,  Tetsuya Fujiwara

IPC: H03L7/085 ,  G01R31/317 ,  H03K3/037 ,  H03K19/20 ,  H03K21/08

Abstract: The present technology relates to a first edge detector that detects whether there is an edge of a second clock signal in one cycle of a first clock signal. A second edge detector detects whether there is an edge of the first clock signal in one cycle of the second clock signal. The logic circuit performs a logical operation on a detection result from the first edge detector and a detection result from the second edge detector. The present technology can be applied to a circuit or the like that detects a locked state of a PLL circuit, for example.

公开(公告)号：US10687295B2

公开(公告)日：2020-06-16

申请号：US15735456

申请日：2016-06-17

Applicant: Sony Corporation

Inventor： Hiroaki Nakano ,  Hiroaki Fujita ,  Uichiro Omae ,  Tetsuya Fujiwara ,  Hiroya Yamamoto

IPC: H04W56/00 ,  H04B5/00 ,  H04L27/06 ,  H04L27/04 ,  H04L7/00 ,  H04L27/00 ,  H04L7/033 ,  H04W4/80 ,  H04L27/34

Abstract: A communication device of the disclosure includes a phase synchronizer, a first modulator, and a detector. The phase synchronizer generates a second signal on a basis of a first signal received from a communication partner. The first modulator is able to modulate the first signal on a basis of the second signal. The detector detects that synchronization between the first signal and the second signal is lost.

公开(公告)号：US20200186254A1

公开(公告)日：2020-06-11

申请号：US16703149

申请日：2019-12-04

Applicant: Sony Corporation

Inventor： Hiroaki Fujita ,  Hiroaki Nakano ,  Uichiro Omae ,  Tetsuya Fujiwara

IPC: H04B10/556 ,  H04B5/00 ,  H04W88/02 ,  H04W52/42 ,  H04W52/10 ,  H04W52/08

Abstract: A communication device of the disclosure includes a phase synchronizer, a modulator, and a controller. The phase synchronizer generates a second signal on a basis of a first signal received from a communication partner by selectively performing one of a closed loop operation and an open loop operation. The modulator is able to modulate the first signal on a basis of the second signal. The controller controls operations of the phase synchronizer and the modulator.

公开(公告)号：US20180160383A1

公开(公告)日：2018-06-07

申请号：US15735456

申请日：2016-06-17

Applicant: Sony Corporation

Inventor： Hiroaki Nakano ,  Hiroaki Fujita ,  Uichiro Omae ,  Tetsuya Fujiwara ,  Hiroya Yamamoto

IPC: H04W56/00

Abstract: A communication device of the disclosure includes a phase synchronizer, a first modulator, and a detector. The phase synchronizer generates a second signal on a basis of a first signal received from a communication partner. The first modulator is able to modulate the first signal on a basis of the second signal. The detector detects that synchronization between the first signal and the second signal is lost.

公开(公告)号：US10523330B2

公开(公告)日：2019-12-31

申请号：US15580135

申请日：2016-06-17

Applicant: Sony Corporation

Inventor： Hiroaki Fujita ,  Hiroaki Nakano ,  Uichiro Omae ,  Tetsuya Fujiwara

IPC: H04B10/556 ,  H04W52/08 ,  H04W52/10 ,  H04W52/42 ,  H04W88/02

Abstract: A communication device of the disclosure includes a phase synchronizer, a modulator, and a controller. The phase synchronizer generates a second signal on a basis of a first signal received from a communication partner by selectively performing one of a closed loop operation and an open loop operation. The modulator is able to modulate the first signal on a basis of the second signal. The controller controls operations of the phase synchronizer and the modulator.

公开(公告)号：US20180145763A1

公开(公告)日：2018-05-24

申请号：US15580135

申请日：2016-06-17

Applicant: Sony Corporation

Inventor： Hiroaki Fujita ,  Hiroaki Nakano ,  Uichiro Omae ,  Tetsuya Fujiwara

IPC: H04B10/556 ,  H04W88/02 ,  H04W52/08 ,  H04W52/10 ,  H04W52/42

CPC classification number: H04B10/5563 ,  H04B5/0031 ,  H04B5/0081 ,  H04W52/08 ,  H04W52/10 ,  H04W52/42 ,  H04W88/021

Abstract: A communication device of the disclosure includes a phase synchronizer, a modulator, and a controller. The phase synchronizer generates a second signal on a basis of a first signal received from a communication partner by selectively performing one of a closed loop operation and an open loop operation. The modulator is able to modulate the first signal on a basis of the second signal. The controller controls operations of the phase synchronizer and the modulator.