公开(公告)号：US09294107B2

公开(公告)日：2016-03-22

申请号：US14459934

申请日：2014-08-14

Applicant: Sony Corporation

Inventor： Norihito Suzuki

IPC: H03L7/06 ,  H03L7/093 ,  H03L7/089

CPC classification number: H03L7/093 ,  H03L7/0891

Abstract: Provided is a phase locked loop circuit that includes: a phase comparison section configured to compare a phase of a first clock signal and a phase of a second clock signal; a loop filter configured to generate a control voltage based on a comparison result by the phase comparison section; and a clock signal generation section configured to generate a clock signal having a frequency corresponding to the control voltage, and output the clock signal as the second clock signal. The loop filter includes a first resistor inserted between a first node on a signal path and a second node, a first capacitor inserted between the second node and a first DC power supply, a first switch inserted between the second node and a third node on the signal path, and a second capacitor inserted between the third node and a second DC power supply.

Abstract translation: 提供一种锁相环电路，其包括：相位比较部，被配置为比较第一时钟信号的相位和第二时钟信号的相位; 环路滤波器，被配置为基于所述相位比较部分的比较结果产生控制电压; 以及时钟信号生成部，被配置为生成具有与所述控制电压对应的频率的时钟信号，并输出所述时钟信号作为所述第二时钟信号。 环路滤波器包括插入在信号路径上的第一节点和第二节点之间的第一电阻器，插在第二节点和第一直流电源之间的第一电容器，插在第二节点和第二节点之间的第三节点的第一开关 信号路径，以及插在第三节点和第二直流电源之间的第二电容器。

公开(公告)号：US09281826B2

公开(公告)日：2016-03-08

申请号：US14626109

申请日：2015-02-19

Applicant: Sony Corporation

Inventor： Tetsuya Fujiwara ,  Yusuke Tanaka ,  Norihito Suzuki

IPC: H03B5/12 ,  H03L7/06

CPC classification number: H03L7/06 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/005 ,  H03B2201/011 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03J2200/10

Abstract: A circuit includes first and second capacitances arranged on a first path that connects first and second terminals; a first switch arranged between the first capacitance and the second capacitance; a second switch arranged on a second path that connects a reference voltage section and a first node formed between the first capacitance and the first switch; a third switch arranged on a third path that connects the section and a second node formed between the second capacitance and the first switch; a first resistance arranged on a fourth path that connects the first node and a third node formed between the first terminal and the first capacitance; a second resistance arranged on a fifth path that connects the second node and a fourth node formed between the second terminal and the second capacitance; a fourth switch on the fourth path; and a fifth switch on the fifth path.

Abstract translation: 电路包括布置在连接第一和第二端子的第一路径上的第一和第二电容; 布置在所述第一电容和所述第二电容之间的第一开关; 布置在连接参考电压部分和形成在第一电容和第一开关之间的第一节点的第二路径上的第二开关; 布置在连接所述部分的第三路径上的第三开关和形成在所述第二电容和所述第一开关之间的第二节点; 布置在连接所述第一节点和形成在所述第一端子和所述第一电容之间的第三节点的第四路径上的第一电阻; 布置在连接所述第二节点的第五路径上的第二电阻和形成在所述第二端子和所述第二电容之间的第四节点; 第四路上的第四个开关; 和第五路上的第五个开关。

公开(公告)号：US20150256185A1

公开(公告)日：2015-09-10

申请号：US14626109

申请日：2015-02-19

Applicant: SONY CORPORATION

Inventor： Tetsuya Fujiwara ,  Yusuke Tanaka ,  Norihito Suzuki

IPC: H03L7/06 ,  H03K3/36

CPC classification number: H03L7/06 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/005 ,  H03B2201/011 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03J2200/10

Abstract: A circuit includes first and second capacitances arranged on a first path that connects first and second terminals; a first switch arranged between the first capacitance and the second capacitance; a second switch arranged on a second path that connects a reference voltage section and a first node formed between the first capacitance and the first switch; a third switch arranged on a third path that connects the section and a second node formed between the second capacitance and the first switch; a first resistance arranged on a fourth path that connects the first node and a third node formed between the first terminal and the first capacitance; a second resistance arranged on a fifth path that connects the second node and a fourth node formed between the second terminal and the second capacitance; a fourth switch on the fourth path; and a fifth switch on the fifth path.

Abstract translation: 电路包括布置在连接第一和第二端子的第一路径上的第一和第二电容; 布置在所述第一电容和所述第二电容之间的第一开关; 布置在连接参考电压部分和形成在第一电容和第一开关之间的第一节点的第二路径上的第二开关; 布置在连接所述部分的第三路径上的第三开关和形成在所述第二电容和所述第一开关之间的第二节点; 布置在连接所述第一节点和形成在所述第一端子和所述第一电容之间的第三节点的第四路径上的第一电阻; 布置在连接所述第二节点的第五路径上的第二电阻和形成在所述第二端子和所述第二电容之间的第四节点; 第四路上的第四个开关; 和第五路上的第五个开关。