公开(公告)号：US20170019650A1

公开(公告)日：2017-01-19

申请号：US15266287

申请日：2016-09-15

Applicant: Sony Corporation

Inventor： Ryota Kosakai ,  Katsutoshi Aiki ,  Nobuyuki Sato ,  Hiroki Nagahama ,  Masatoshi Sase ,  Yutaka Yoneda

IPC: H04N9/73 ,  H04N9/69 ,  H04N5/232 ,  H04N7/01 ,  G11B27/00 ,  H04N9/87 ,  H04N9/79 ,  H04N5/378 ,  G11B31/00 ,  H04N9/04 ,  H04N9/80

CPC classification number: H04N9/735 ,  G11B27/005 ,  G11B27/031 ,  G11B31/006 ,  H04N5/232 ,  H04N5/23232 ,  H04N5/23245 ,  H04N5/23293 ,  H04N5/378 ,  H04N5/77 ,  H04N5/772 ,  H04N5/783 ,  H04N5/91 ,  H04N7/0105 ,  H04N7/0127 ,  H04N9/045 ,  H04N9/69 ,  H04N9/7904 ,  H04N9/80 ,  H04N9/87

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

Abstract translation: 在高速图像捕获状态下，不需要相机信号处理电路来以高屏幕速率但以常规屏幕速率执行信号处理。 在高速图像拍摄模式中，从图像传感器101接收的240fps的原始数据通过转换处理部分201和记录装置控制电路210记录在记录装置111上。已被抽取和尺寸转换的原始数据 通过预处理电路202被提供给相机信号处理电路203，并且正在捕获的图像被显示在已经执行了相机处理的信号的显示部分112上。 在再现状态下，根据显示部分112的显示性能，并且已经被读取的原始数据被处理前处理电路202处理，以低屏幕速率从记录装置111读出原始数据， 相机信号处理电路203和再现图像由显示部分112显示。

公开(公告)号：US20160381339A1

公开(公告)日：2016-12-29

申请号：US14901770

申请日：2014-09-01

Applicant: SONY CORPORATION

Inventor： Seijiro Inaba ,  Ryota Kosakai

IPC: H04N9/82 ,  H04N9/87 ,  G11B27/031 ,  G06T7/20 ,  G06T7/00 ,  G11B27/34

CPC classification number: H04N9/8227 ,  G06T7/292 ,  G06T7/70 ,  G06T2207/30244 ,  G11B27/031 ,  G11B27/34 ,  H04N5/247 ,  H04N5/262 ,  H04N5/2627 ,  H04N9/09 ,  H04N9/87

Abstract: A method for processing image information has accessing position information associated with images, identifying a position sequence that provides a series of locations along a pathway corresponding to a subject, and displaying the images in an order of the position sequence. The position sequence is adjusted based on movement of the subject.

Abstract translation: 用于处理图像信息的方法具有与图像相关联的访问位置信息，识别沿着与对象相对应的路径提供一系列位置的位置序列，并且以所述位置顺序的顺序显示图像。 基于被摄体的移动来调整位置顺序。

公开(公告)号：US09538153B1

公开(公告)日：2017-01-03

申请号：US15266287

申请日：2016-09-15

Applicant: Sony Corporation

Inventor： Ryota Kosakai ,  Katsutoshi Aiki ,  Nobuyuki Sato ,  Hiroki Nagahama ,  Masatoshi Sase ,  Yutaka Yoneda

IPC: H04N9/73 ,  H04N9/04 ,  H04N9/69 ,  H04N5/232 ,  H04N7/01 ,  H04N9/80 ,  H04N9/87 ,  H04N9/79 ,  H04N5/378 ,  G11B31/00 ,  G11B27/00

CPC classification number: H04N9/735 ,  G11B27/005 ,  G11B27/031 ,  G11B31/006 ,  H04N5/232 ,  H04N5/23232 ,  H04N5/23245 ,  H04N5/23293 ,  H04N5/378 ,  H04N5/77 ,  H04N5/772 ,  H04N5/783 ,  H04N5/91 ,  H04N7/0105 ,  H04N7/0127 ,  H04N9/045 ,  H04N9/69 ,  H04N9/7904 ,  H04N9/80 ,  H04N9/87

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

Abstract translation: 在高速图像捕获状态下，不需要相机信号处理电路来以高屏幕速率但以常规屏幕速率执行信号处理。 在高速图像拍摄模式中，从图像传感器101接收的240fps的原始数据通过转换处理部分201和记录装置控制电路210记录在记录装置111上。已被抽取和尺寸转换的原始数据 通过预处理电路202被提供给相机信号处理电路203，并且正在捕获的图像被显示在已经执行了相机处理的信号的显示部分112上。 在再现状态下，根据显示部分112的显示性能，并且已经被读取的原始数据被处理前处理电路202处理，以低屏幕速率从记录装置111读出原始数据， 相机信号处理电路203和再现图像由显示部分112显示。

公开(公告)号：US10986323B2

公开(公告)日：2021-04-20

申请号：US16888224

申请日：2020-05-29

Applicant: Sony Corporation

Inventor： Ryota Kosakai ,  Katsutoshi Aiki ,  Nobuyuki Sato ,  Hiroki Nagahama ,  Masatoshi Sase ,  Yutaka Yoneda

IPC: H04N5/232 ,  H04N9/73 ,  H04N5/77 ,  H04N7/01 ,  H04N9/04 ,  H04N5/783 ,  G11B31/00 ,  H04N5/378 ,  H04N5/91 ,  G11B27/00 ,  G11B27/031 ,  H04N9/69 ,  H04N9/79 ,  H04N9/80 ,  H04N9/87

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing, section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-convert d are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

公开(公告)号：US20170230629A1

公开(公告)日：2017-08-10

申请号：US15581208

申请日：2017-04-28

Applicant: Sony Corporation

Inventor： Ryota Kosakai ,  Katsutoshi Aiki ,  Nobuyuki Sato ,  Hiroki Nagahama ,  Masatoshi Sase ,  Yutaka Yoneda

IPC: H04N9/73 ,  H04N9/69 ,  H04N5/77 ,  H04N7/01 ,  H04N5/232 ,  H04N9/87 ,  G11B27/00 ,  G11B31/00 ,  H04N9/04 ,  H04N9/79

CPC classification number: H04N9/735 ,  G11B27/005 ,  G11B27/031 ,  G11B31/006 ,  H04N5/232 ,  H04N5/23232 ,  H04N5/23245 ,  H04N5/23293 ,  H04N5/378 ,  H04N5/77 ,  H04N5/772 ,  H04N5/783 ,  H04N5/91 ,  H04N7/0105 ,  H04N7/0127 ,  H04N9/045 ,  H04N9/69 ,  H04N9/7904 ,  H04N9/80 ,  H04N9/87

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

公开(公告)号：US20200296342A1

公开(公告)日：2020-09-17

申请号：US16888224

申请日：2020-05-29

Applicant: Sony Corporation

Inventor： Ryota Kosakai ,  Katsutoshi Aiki ,  Nobuyuki Sato ,  Hiroki Nagahama ,  Masatoshi Sase ,  Yutaka Yoneda

IPC: H04N9/73 ,  H04N5/77 ,  H04N5/232 ,  H04N7/01 ,  H04N5/783 ,  G11B31/00 ,  H04N5/378 ,  H04N5/91 ,  G11B27/00 ,  G11B27/031 ,  H04N9/04 ,  H04N9/69 ,  H04N9/79 ,  H04N9/80 ,  H04N9/87

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing, section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-convert d are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

公开(公告)号：US20190281268A1

公开(公告)日：2019-09-12

申请号：US16391771

申请日：2019-04-23

Applicant: Sony Corporation

Inventor： Ryota Kosakai ,  Katsutoshi Aiki ,  Nobuyuki Sato ,  Hiroki Nagahama ,  Masatoshi Sase ,  Yutaka Yoneda

IPC: H04N9/73 ,  G11B27/00 ,  H04N9/87 ,  H04N9/80 ,  H04N9/79 ,  H04N9/69 ,  H04N9/04 ,  H04N7/01 ,  H04N5/91 ,  H04N5/783 ,  H04N5/77 ,  H04N5/378 ,  H04N5/232 ,  G11B31/00 ,  G11B27/031

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

公开(公告)号：US10313648B2

公开(公告)日：2019-06-04

申请号：US15855060

申请日：2017-12-27

Applicant: Sony Corporation

Inventor： Ryota Kosakai ,  Katsutoshi Aiki ,  Nobuyuki Sato ,  Hiroki Nagahama ,  Masatoshi Sase ,  Yutaka Yoneda

IPC: H04N5/932 ,  H04N9/73 ,  H04N5/232 ,  H04N5/783 ,  H04N7/01 ,  G11B31/00 ,  H04N5/77 ,  H04N5/378 ,  H04N5/91 ,  G11B27/00 ,  G11B27/031 ,  H04N9/04 ,  H04N9/69 ,  H04N9/79 ,  H04N9/80 ,  H04N9/87

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

公开(公告)号：US09661291B2

公开(公告)日：2017-05-23

申请号：US15001442

申请日：2016-01-20

Applicant: Sony Corporation

Inventor： Ryota Kosakai ,  Katsutoshi Aiki ,  Nobuyuki Sato ,  Hiroki Nagahama ,  Masatoshi Sase ,  Yutaka Yoneda

IPC: H04N5/932 ,  H04N9/73 ,  H04N5/232 ,  H04N5/783 ,  G11B31/00 ,  H04N5/77 ,  H04N5/378 ,  H04N5/91 ,  G11B27/00 ,  G11B27/031 ,  H04N9/04 ,  H04N9/69 ,  H04N9/79 ,  H04N9/80 ,  H04N9/87 ,  H04N7/01

CPC classification number: H04N9/735 ,  G11B27/005 ,  G11B27/031 ,  G11B31/006 ,  H04N5/232 ,  H04N5/23232 ,  H04N5/23245 ,  H04N5/23293 ,  H04N5/378 ,  H04N5/77 ,  H04N5/772 ,  H04N5/783 ,  H04N5/91 ,  H04N7/0105 ,  H04N7/0127 ,  H04N9/045 ,  H04N9/69 ,  H04N9/7904 ,  H04N9/80 ,  H04N9/87

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

公开(公告)号：US11388380B2

公开(公告)日：2022-07-12

申请号：US17203471

申请日：2021-03-16

Applicant: Sony Corporation

Inventor： Ryota Kosakai ,  Katsutoshi Aiki ,  Nobuyuki Sato ,  Hiroki Nagahama ,  Masatoshi Sase ,  Yutaka Yoneda

IPC: H04N5/77 ,  H04N9/73 ,  H04N5/232 ,  H04N7/01 ,  H04N9/04 ,  H04N5/783 ,  G11B31/00 ,  H04N5/378 ,  H04N5/91 ,  G11B27/00 ,  G11B27/031 ,  H04N9/69 ,  H04N9/79 ,  H04N9/80 ,  H04N9/87

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.