公开(公告)号：US09429981B2

公开(公告)日：2016-08-30

申请号：US13784909

申请日：2013-03-05

Applicant: ST-Ericsson SA

Inventor： Håkan Persson

IPC: G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G06F1/32

CPC classification number: G06F1/06 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads.

Abstract translation: 通过将具有不同相对相位的时钟信号施加到CPU的不同部分，由于CPU内部的逻辑切换引起的高频电流瞬变被减少。 这降低了电流变化的幅度，并因此降低了对电源电压的感应。 在一些实施例中，多核CPU内的不同CPU内核以不同的时钟相位计时。 另外，提供了在存在大的OCV效应的情况下用于低等待时间通信的方法和电路。 低延迟通信可以基于FIFO。 标记用于指示安全点在更新和读取发射机和接收机之间的信号。 选通在中央时钟发生模块中产生。 选通机制用于在发送器和接收器之间传送读取和写入指针，同时使用允许数据写入与相应数据读取异步的FIFO数据数据传输有效载荷数据。

公开(公告)号：US20140258765A1

公开(公告)日：2014-09-11

申请号：US13784909

申请日：2013-03-05

Applicant: ST-ERICSSON SA

Inventor： Håkan Persson

IPC: G06F1/06

CPC classification number: G06F1/06 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads.

Abstract translation: 通过将具有不同相对相位的时钟信号施加到CPU的不同部分，由于CPU内部的逻辑切换引起的高频电流瞬变被减少。 这降低了电流变化的幅度，并因此降低了对电源电压的感应。 在一些实施例中，多核CPU内的不同CPU内核以不同的时钟相位计时。 另外，提供了在存在大的OCV效应的情况下用于低等待时间通信的方法和电路。 低延迟通信可以基于FIFO。 标记用于指示安全点在更新和读取发射机和接收机之间的信号。 选通在中央时钟发生模块中产生。 选通机制用于在发送器和接收器之间传送读取和写入指针，同时使用允许数据写入与相应数据读取异步的FIFO数据数据传输有效载荷数据。