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公开(公告)号：US09219491B2
公开(公告)日：2015-12-22
申请号：US14412747
申请日：2013-07-17
Applicant: ST-Ericsson SA
Inventor： Alberto Minuti , Francesca Girardi , Germano Nicollini , Marco Zamprogno
Abstract: An electronic analog-to-digital conversion device includes an analog-to-digital conversion block having a first input for receiving a voltage signal to be converted based on a reference voltage signal provided to a second input, and an input block connected to the first input of the analog-to-digital conversion block. The input block receives an input signal at a first resistive network connected to a second resistive network, which is then connected to a reference potential. The input block also includes an active network connected between an output of the first resistive network and the first input of the analog-to-digital conversion block. The active network has a first input terminal directly connected to the second input of the analog-to-digital conversion block for receiving the same reference voltage signal so that the input voltage signal received at a second input of the active network is processed based on the reference voltage signal.
Abstract translation: 一种电子模拟 - 数字转换装置，包括具有第一输入的模数转换块，该第一输入用于基于提供给第二输入端的参考电压信号接收要转换的电压信号;以及输入模块，连接到第一输入端 输入模数转换块。 输入块在连接到第二电阻网络的第一电阻网络处接收输入信号，该第二电阻网络然后连接到参考电位。 输入块还包括连接在第一电阻网络的输出端和模数转换块的第一输入端之间的有源网络。 有源网络具有直接连接到模数转换块的第二输入的第一输入端，用于接收相同的参考电压信号，使得在有源网络的第二输入处接收的输入电压信号基于 参考电压信号。
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公开(公告)号：US09024798B2
公开(公告)日：2015-05-05
申请号：US14360860
申请日：2012-11-08
Applicant: ST-Ericsson SA
Inventor： Marco Zamprogno , Francesca Girardi , Alberto Minuti
CPC classification number: H03M1/466 , H03M1/0697 , H03M1/0845 , H03M1/42 , H03M1/46
Abstract: According to a method of Successive Approximation Register (SAR) analog to digital conversion, N+1 SAR cycles are performed to obtain an output digital code having N bits. An analog signal is sampled and obtained. After execution of the first N−1 SAR cycles, the Nth SAR cycle is performed by setting a Nth tentative analog signal corresponding to a provisional digital code and comparing the Nth tentative analog signal with the sampled analog signal to obtain a Nth comparison result. The (N+1)th SAR cycle is performed by setting a (N+1)th tentative analog signal based on the Nth comparison result, comparing the (N+1)th tentative analog signal with the sampled analog signal to obtain a second comparison result, and correcting the provisional digital code based on the (N+1)th comparison result to obtain the output digital code. The Nth and (N+1)th SAR cycles each comprise a plurality sub-comparisons and yield a set of sub-results.
Abstract translation: 根据连续近似寄存器（SAR）模数转换的方法，执行N + 1个SAR周期以获得具有N位的输出数字码。 对模拟信号进行采样和获取。 在执行第一N-1个SAR周期之后，通过设置与临时数字代码对应的第N个暂定模拟信号并将第N个初步模拟信号与采样的模拟信号进行比较来获得第N个比较结果来执行第N个SAR周期。 通过基于第N个比较结果设置第（N + 1）个暂定模拟信号，比较第（N + 1）个SAR周期，将第（N + 1）个暂定模拟信号与采样的模拟信号进行比较，以获得第二 比较结果，并且基于第（N + 1）比较结果来校正临时数字码，以获得输出数字码。 第N和第（N + 1）个SAR周期各自包括多个子比较并产生一组子结果。
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公开(公告)号：US20150171881A1
公开(公告)日：2015-06-18
申请号：US14412747
申请日：2013-07-17
Applicant: ST-Ericsson SA
Inventor： Alberto Minuti , Francesca Girardi , Germano Nicollini , Marco Zamprogno
IPC: H03M1/12
Abstract: The present disclosure relates to an electronic analog-to-digital conversion device (100) which comprises: an analog-to-digital conversion block (101) having a first input (1) for receiving a voltage signal (Vout) to be converted on the basis of a reference voltage signal (VREF) provided to a second input (2) of the same analog-to-digital conversion block (101);—an input block (102) having an input terminal (3) and an output terminal (4) connected to the first input (1) of the analog-to-digital conversion block (101). The input block (102) is arranged for processing an input voltage signal (Vin) applied to the input terminal (3) to generate the voltage signal (Vout) at the output terminal (4). The input block (102) comprises:—a first resistive network (103) operatively connected to both the input terminal (3) and the output terminal (4);—a second resistive network (104) connected between the output terminal (4) and a reference potential (GND). The input block (102) is characterized by comprising an active network (105) connected between an output node (5) of the first resistive network (103) and the output terminal (4). The active network (105) has a first input terminal (6) directly connected to the second input (2) of the analog-to-digital conversion block (101) for receiving the same reference voltage signal (VREF) provided to the second input (2) so that the input voltage signal (Vin) is processed by the input block (102) on the basis of such reference voltage signal (VREF).
Abstract translation: 本公开涉及一种电子模数转换装置（100），其包括：模数转换块（101），具有用于接收要转换的电压信号（Vout）的第一输入（1） 提供给同一模数转换块（101）的第二输入（2）的参考电压信号（VREF）的基础; - 输入块（102），具有输入端（3）和输出端 （4）连接到模数转换块（101）的第一输入（1）。 输入块（102）被布置用于处理施加到输入端子（3）的输入电压信号（Vin），以在输出端子（4）产生电压信号（Vout）。 输入块（102）包括： - 第一电阻网络（103），可操作地连接到输入端（3）和输出端（4）; - 第二电阻网（104），连接在输出端（4） 和参考电位（GND）。 输入块（102）的特征在于包括连接在第一电阻网络（103）的输出节点（5）和输出端（4）之间的有源网络（105）。 有源网络（105）具有直接连接到模拟 - 数字转换块（101）的第二输入（2）的第一输入端（6），用于接收提供给第二输入端的相同参考电压信号（VREF） （2），使得输入电压信号（Vin）由输入块（102）基于这样的参考电压信号（VREF）来处理。
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公开(公告)号：US20150084801A1
公开(公告)日：2015-03-26
申请号：US14360860
申请日：2012-11-08
Applicant: ST-Ericsson SA
Inventor： Marco Zamprogno , Francesca Girardi , Alberto Minuti
CPC classification number: H03M1/466 , H03M1/0697 , H03M1/0845 , H03M1/42 , H03M1/46
Abstract: According to a method of Successive Approximation Register (SAR) analog to digital conversion, N+1 SAR cycles are performed to obtain an output digital code having N bits. An analog signal is sampled and obtained. After execution of the first N−1 SAR cycles, the Nth SAR cycle is performed by setting a Nth tentative analog signal corresponding to a provisional digital code and comparing the Nth tentative analog signal with the sampled analog signal to obtain a Nth comparison result. The (N+1)th SAR cycle is performed by setting a (N+1)th tentative analog signal based on the Nth comparison result, comparing the (N+1)th tentative analog signal with the sampled analog signal to obtain a second comparison result, and correcting the provisional digital code based on the (N+1)th comparison result to obtain the output digital code. The Nth and (N+1)th SAR cycles each comprise a plurality sub-comparisons and yield a set of sub-results.
Abstract translation: 根据连续近似寄存器（SAR）模数转换的方法，执行N + 1个SAR周期以获得具有N位的输出数字码。 对模拟信号进行采样和获取。 在执行第一N-1个SAR周期之后，通过设置与临时数字代码对应的第N个暂定模拟信号并将第N个初步模拟信号与采样的模拟信号进行比较来获得第N个比较结果来执行第N个SAR周期。 通过基于第N个比较结果设置第（N + 1）个暂定模拟信号，比较第（N + 1）个SAR周期，将第（N + 1）个暂定模拟信号与采样的模拟信号进行比较，以获得第二 比较结果，并且基于第（N + 1）比较结果来校正临时数字码，以获得输出数字码。 第N和第（N + 1）个SAR周期各自包括多个子比较并产生一组子结果。
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