公开(公告)号：US08729687B2

公开(公告)日：2014-05-20

申请号：US13649834

申请日：2012-10-11

Applicant: STATS ChipPAC Ltd.

Inventor： Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/31 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Abstract translation: 提供了一种堆叠集成电路封装包装系统，包括形成第一外部互连; 在第一外部互连下方安装第一集成电路管芯; 在第一集成电路管芯上以不在第一外部互连上的偏移配置堆叠第二集成电路管芯; 将所述第一集成电路管芯与所述第一外部互连件连接; 并且将所述第二集成电路管芯与所述第一外部互连件封装，并且所述第一集成电路管芯部分地露出。