公开(公告)号：US20240021566A1

公开(公告)日：2024-01-18

申请号：US17812836

申请日：2022-07-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： WooSoon Kim ,  JoonYoung Choi ,  YoungCheol Kim ,  KyungOe Kim

IPC: H01L23/00 ,  H01L25/16 ,  H01L21/56

CPC classification number: H01L24/32 ,  H01L24/94 ,  H01L24/97 ,  H01L24/16 ,  H01L24/73 ,  H01L25/167 ,  H01L24/27 ,  H01L21/563 ,  H01L2924/12043 ,  H01L2924/13056 ,  H01L2924/15311 ,  H01L2924/182 ,  G02B6/13

Abstract: A semiconductor device has a semiconductor die with a sensitive area. A dam wall is formed over the semiconductor die proximate to the sensitive area. In one embodiment, the dam wall has a vertical segment and side wings. The dam wall can have a plurality of rounded segments integrated with a plurality of vertical segments as a unitary body. Alternatively, the dam wall has a plurality of separate vertical segments arranged in two or more overlapping rows. A plurality of conductive posts is formed over the semiconductor die. An electrical component is disposed over the semiconductor die. The semiconductor die and electrical component are disposed over a substrate. An insulating layer is formed over the substrate outside the dam wall. An underfill material is deposited between the semiconductor die and substrate. The dam wall and insulating layer inhibit the underfill material from contacting any portion of the sensitive area.