公开(公告)号：US20250006608A1

公开(公告)日：2025-01-02

申请号：US18344920

申请日：2023-06-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Linda Pei Ee Chua ,  Kai Chong Chan ,  Rowena Zarate ,  Marites Roque ,  Yi Jing Eric Chong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has an electrical component and an e-bar structure disposed to a side of the electrical component. An encapsulant is deposited over the electrical component and e-bar structure. An RDL is formed over the electrical component, encapsulant, and e-bar structure. The e-bar structure has a core layer, a first conductive layer formed over a first surface of the core layer, and a second conductive layer formed over a second surface of the core layer. The second conductive layer includes a thickness greater than the first conductive layer. The RDL has an insulating layer formed over the electrical component and encapsulant, and a conductive layer formed over the insulating layer. A bump is formed over a contact pad of the e-bar structure opposite the RDL. A contact pad of the electrical component is electrically connected to the RDL opposite the bump.

公开(公告)号：US20250118643A1

公开(公告)日：2025-04-10

申请号：US18483433

申请日：2023-10-09

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yi Jing Eric Chong ,  Marites Roque ,  Rowena Zarate ,  Linda Pei Ee Chua ,  Kai Chong Chan

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device has a first substrate with a surface. A thickness of the first substrate is less than 120 micrometers. The surface undergoes a grinding operation. The surface of the first substrate is then polished to produce a polished surface. The first substrate is singulated into a plurality of semiconductor die. The semiconductor die is over an interposer. The interposer has a second substrate and a conductive via formed through the second substrate. The interposer further has a first insulating layer formed over a first surface of the second substrate, first conductive layer formed over the first surface, second insulating layer formed over a second surface of the second substrate, second conductive layer formed over the second surface, and bump formed over the second conductive layer. An underfill material is deposited around the semiconductor die. The polished surface inhibits progression of the underfill material onto the polished surface.

公开(公告)号：US20250112078A1

公开(公告)日：2025-04-03

申请号：US18479276

申请日：2023-10-02

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Tack Chee Yong ,  Yi Jing Eric Chong ,  Kok Lim Jason Ng ,  Linda Pei Ee Chua

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/68

Abstract: A semiconductor manufacturing equipment has a wafer tape including a plurality of alignment holes formed through the wafer tape. A semiconductor wafer is disposed over the wafer tape. The semiconductor wafer includes a circular or rectangular form-factor. A light source is disposed under the wafer tape. The semiconductor wafer is misaligned on the wafer tape with light passing through one or more alignment holes. The semiconductor wafer is centered on the wafer tape with no light passing through one or more alignment holes. The wafer tape has a plurality of wafer alignment markings for different size semiconductor wafers. A light detector is disposed over the semiconductor wafer to detect light passing through the wafer tape. A control arm can be attached to the semiconductor wafer to provide the ability to move the semiconductor wafer in response to a control signal from the light detector.