公开(公告)号：US20240105630A1

公开(公告)日：2024-03-28

申请号：US17936037

申请日：2022-09-28

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Ching Meng Fang ,  Hin Hwa Goh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/5385 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/162 ,  H01L25/165 ,  H01L21/563 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/95001 ,  H01L2924/182 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001

Abstract: A semiconductor device has a first RDL substrate with first conductive pillars formed over a first surface of the first RDL substrate. A first electrical component is disposed over the first surface of the first RDL substrate. A hybrid substrate is bonded to the first RDL substrate. An encapsulant is deposited around the hybrid substrate and first RDL substrate with the first conductive pillars and first electrical component embedded within the encapsulant. A second RDL substrate with second conductive pillars formed over the second RDL substrate and second electrical component disposed over the second RDL substrate can be bonded to the hybrid substrate. A second RDL can be formed over a second surface of the first RDL substrate. A third electrical component is disposed over a second surface of the first RDL substrate. A shielding frame is disposed over the third electrical component.

公开(公告)号：US20240071885A1

公开(公告)日：2024-02-29

申请号：US17823827

申请日：2022-08-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Jian Zuo ,  Hin Hwa Goh

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/3511

Abstract: A semiconductor device has a first hybrid substrate with a first thickness, and a second hybrid substrate with a second thickness different from the first thickness of the first hybrid substrate. An encapsulant is deposited around the first hybrid substrate and second hybrid substrate. A portion of the first hybrid substrate and a portion of the second hybrid substrate and a portion of the encapsulant can be removed after encapsulation to achieve uniform thickness for the first hybrid substate and second hybrid substrate. The first hybrid substrate has an embedded substrate, a first interconnect structure formed over a first surface of the embedded substrate, and a second interconnect structure formed over a second surface of the embedded substrate opposite the first surface of the embedded substrate. A plurality of conductive pillars is formed over the first interconnect structure. A plurality of conductive vias is formed through the embedded substrate.

公开(公告)号：US20170330840A1

公开(公告)日：2017-11-16

申请号：US15664734

申请日：2017-07-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Byung Joon Han ,  Rajendra D. Pendse ,  Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Linda Pei Ee Chua

IPC: H01L23/552 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component.

公开(公告)号：US20250006608A1

公开(公告)日：2025-01-02

申请号：US18344920

申请日：2023-06-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Linda Pei Ee Chua ,  Kai Chong Chan ,  Rowena Zarate ,  Marites Roque ,  Yi Jing Eric Chong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has an electrical component and an e-bar structure disposed to a side of the electrical component. An encapsulant is deposited over the electrical component and e-bar structure. An RDL is formed over the electrical component, encapsulant, and e-bar structure. The e-bar structure has a core layer, a first conductive layer formed over a first surface of the core layer, and a second conductive layer formed over a second surface of the core layer. The second conductive layer includes a thickness greater than the first conductive layer. The RDL has an insulating layer formed over the electrical component and encapsulant, and a conductive layer formed over the insulating layer. A bump is formed over a contact pad of the e-bar structure opposite the RDL. A contact pad of the electrical component is electrically connected to the RDL opposite the bump.

公开(公告)号：US20170062390A1

公开(公告)日：2017-03-02

申请号：US15349838

申请日：2016-11-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Linda Pei Ee Chua ,  Byung Tai Do ,  Reza A. Pagaila

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/78 ,  H01L21/288 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/288 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/17 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L29/40 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32502 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.

Abstract translation: 半导体器件具有在载体上形成的导电柱。 第一半导体管芯安装在载体之间的导电柱之间。 密封剂沉积在第一半导体管芯和载体上并且围绕导电柱。 在第一半导体管芯上的密封剂的第一表面中形成凹部。 凹槽有倾斜或阶梯。 在密封剂的第一表面上形成第一互连结构。 第一互连结构遵循密封剂中的凹部的轮廓。 载体被移除。 在密封剂和第一半导体管芯的第二表面上形成第二互连结构。 第一和第二互连结构电连接到导电柱。 第二半导体管芯安装在凹槽中。 第三半导体管芯安装在凹槽和第二半导体管芯上。

公开(公告)号：US20250140730A1

公开(公告)日：2025-05-01

申请号：US18498494

申请日：2023-10-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  DanFeng Yang ,  Hin Hwa Goh

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01Q1/22

Abstract: A semiconductor device has an electrical component and a first interconnect structure disposed adjacent to the electrical component. The electrical component can be a direct metal bonded semiconductor die or a flipchip semiconductor die. The first interconnect structure can be an interposer unit or a conductive pillar. A split antenna is disposed over the electrical component and first interconnect structure. The split antenna has a first antenna section and a second antenna section with an adhesive material disposed between the first antenna section and second antenna section. A second interconnect structure is formed over the electrical component and first interconnect structure. The second interconnect structure has one or more conductive layers and insulating layers. The first interconnect structure and second interconnect structure provide a conduction path between the electrical component and split antenna. An encapsulant is deposited around the electrical component and first interconnect structure.

公开(公告)号：US20250096095A1

公开(公告)日：2025-03-20

申请号：US18468957

申请日：2023-09-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Peik Eng Ooi ,  Beng Yee Teh ,  Linda Pei Ee Chua

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die to form a reconstituted wafer. A first insulating layer is formed over the reconstituted wafer. A first dummy opening is formed in the first insulating layer. A first conductive layer is formed on the first insulating layer including a first contact pad over the first dummy opening.

公开(公告)号：US20250132291A1

公开(公告)日：2025-04-24

申请号：US18492047

申请日：2023-10-23

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DanFeng Yang ,  Yaojian Lin ,  Linda Pei Ee Chua ,  Kai Chong Chan ,  Jian Zuo

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: A semiconductor device has a first interconnect structure. A first bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the first bridge die. A second interconnect structure is formed over the first bridge die and encapsulant. A second bridge die is disposed over the second interconnect structure.

公开(公告)号：US20250038101A1

公开(公告)日：2025-01-30

申请号：US18357361

申请日：2023-07-24

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Ming-Che Hsieh ,  Linda Pei Ee Chua ,  Yaojian Lin

IPC: H01L23/50 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22

Abstract: A semiconductor device has an electrical component and a plurality of e-bar structures disposed adjacent to the electrical component. An antenna interposer is disposed over a first surface of the e-bar structures. A redistribution layer is formed over a second surface of the e-bar structures opposite the first surface of the e-bar structures. The redistribution layer has a conductive layer and an insulating layer formed over the conductive layer. An encapsulant is deposited over the electrical component. The antenna interposer has a first conductive layer, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the insulating layer. The second conductive layer can be arranged as a plurality of islands or in a serpentine pattern.

公开(公告)号：US20240096807A1

公开(公告)日：2024-03-21

申请号：US17933149

申请日：2022-09-19

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Hin Hwa Goh ,  Jian Zuo

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/5383 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/552 ,  H01L25/16 ,  H01L24/05 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A semiconductor device has an RDL substrate and hybrid substrate with a plurality of bumps. The hybrid substrate is bonded to the RDL substrate. An encapsulant is deposited around the hybrid substrate and RDL substrate with the bumps embedded within the encapsulant. The hybrid substrate has a core substrate, first RDL formed over a first surface of the core substrate, conductive pillars formed over the first RDL, and second RDL over a second surface of the core substrate. A portion of the encapsulant is removed to expose the conductive pillars. The RDL substrate has a carrier and RDL formed over a surface of the carrier. The carrier is removed after bonding the hybrid substrate to the RDL substrate. Alternatively, the RDL substrate has a core substrate, first RDL formed over a first surface of the core substrate, and second RDL formed over a second surface of the core substrate.