公开(公告)号：US20020163027A1

公开(公告)日：2002-11-07

申请号：US10114672

申请日：2002-04-02

Applicant: STMICROELECTRONICS S.A.

Inventor： Thomas Skotnicki ,  Emmanuel Josse

IPC: H01L027/108

CPC classification number: H01L29/66666 ,  H01L29/165 ,  H01L29/7827

Abstract: The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.

Abstract translation: 垂直绝缘栅晶体管包括在半导体衬底上的垂直柱，其顶部包括源极和漏极区中的一个，位于柱的侧面和衬底顶表面上的栅极电介质层，以及半导体 门静置在栅介质层上。 源极和漏极区域中的另一个位于柱PIL的底部，并且绝缘栅极包括搁置在柱的侧面上的隔离的外部部分15和位于源极和漏极区域之间的柱内的隔离的内部部分14 。 隔离的内部部分通过在源极和漏极区域之间延伸的两个连接半导体区域PL1，PL2从隔离的外部部分侧向分离，并形成两个非常细的柱。

公开(公告)号：US20020177265A1

公开(公告)日：2002-11-28

申请号：US10114329

申请日：2002-04-02

Applicant: STMICROELECTRONICS S.A.

Inventor： Thomas Skotnicki ,  Emmanuel Josse

IPC: H01L021/8238

CPC classification number: H01L29/66666 ,  H01L21/2807 ,  H01L21/2815 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/7827

Abstract: The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14S, 14D.

Abstract translation: 垂直晶体管在半导体衬底上包括在顶部具有源极和漏极区中的一个的垂直柱5，源极和漏极区中的另一个位于柱的外围的衬底中，栅极介电层 7位于柱的侧面和基板的顶表面上，以及位于栅极介电层上的半导体栅极。 栅极包括具有搁置在栅极电介质层7上的第一区域800的半导体块和面向源极和漏极区域的至少部分的第二区域90，并且通过电介质腔14S，14D与那些源极和漏极区域分离。