公开(公告)号：US11495310B2

公开(公告)日：2022-11-08

申请号：US17508775

申请日：2021-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Matranga ,  Gianbattista Lo Giudice ,  Rosario Roberto Grasso ,  Alberto Jose' Di Martino

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/14

Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.

公开(公告)号：US11328778B2

公开(公告)日：2022-05-10

申请号：US16925104

申请日：2020-07-09

Applicant: STMicroelectronics S.r.l.

Inventor： Gianbattista Lo Giudice ,  Giovanni Matranga ,  Rosario Roberto Grasso ,  Alberto Jose' Di Martino

IPC: G11C16/14 ,  G06F3/06 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04

Abstract: A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.

公开(公告)号：US20220011943A1

公开(公告)日：2022-01-13

申请号：US16925104

申请日：2020-07-09

Applicant: STMicroelectronics S.r.l.

Inventor： Gianbattista Lo Giudice ,  Giovanni Matranga ,  Rosario Roberto Grasso ,  Alberto Jose' Di Martino

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.

公开(公告)号：US09484872B1

公开(公告)日：2016-11-01

申请号：US14969042

申请日：2015-12-15

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Antonino Conte ,  Alberto Jose' Di Martino

IPC: H03F3/45 ,  H03M1/66 ,  G11C16/12 ,  G11C5/14

CPC classification number: H03F3/45179 ,  G11C5/145 ,  G11C16/12 ,  H03F3/3027 ,  H03F3/45659 ,  H03F3/45748 ,  H03F3/45973 ,  H03F2203/45116 ,  H03F2203/45424 ,  H03F2203/45431 ,  H03M1/66

Abstract: An amplifier circuit may include an input amplification stage comprising a first amplifier having first and second differential inputs and a first output, and a second amplifier having first and second differential inputs and a second output. The amplifier circuit also includes an output amplification stage having first and second inputs respectively coupled to the first and second outputs of the input amplification stage, and an output configured to supply an output voltage based upon the input voltage by an amplification factor. The amplifier circuit comprises a feedback stage with a common-mode control stage configured to implement a comparison between the first differential voltage and the second differential voltage, and a reference voltage, and generate respective regulation currents on the first and second inputs of the output amplification stage to compensate for a common-mode variation of the first differential voltage and the second differential voltage.

Abstract translation: 放大器电路可以包括输入放大级，其包括具有第一和第二差分输入和第一输出的第一放大器，以及具有第一和第二差分输入和第二输出的第二放大器。 放大器电路还包括输出放大级，其具有分别耦合到输入放大级的第一和第二输出的第一和第二输入以及被配置为基于输入电压提供放大因子的输出电压的输出。 放大器电路包括具有共模控制级的反馈级，配置为实现第一差分电压和第二差分电压之间的比较以及参考电压，并且在输出放大的第一和第二输入上产生相应的调节电流 以补偿第一差分电压和第二差分电压的共模变化。