公开(公告)号：US20040202244A1

公开(公告)日：2004-10-14

申请号：US10757368

申请日：2004-01-13

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Agatino Pennisi

IPC: H04B001/66

CPC classification number: G06F13/423 ,  Y02D10/14 ,  Y02D10/151

Abstract: N binary signals are transmitted through a bus of m leads, where m

Abstract translation: 通过在第二信号上对第一信号进行编码，以一串时钟脉冲的节奏通过m引线的总线m

公开(公告)号：US20040103334A1

公开(公告)日：2004-05-27

申请号：US10622835

申请日：2003-07-18

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Francesco Pappalardo ,  Agatino Pennisi

IPC: G06F001/12

CPC classification number: G06F1/06 ,  G06F9/3869

Abstract: A pipeline structure is provided for use in a digital system. The pipeline structure includes stages arranged in a sequence from a first stage for receiving an input of the pipeline structure to a last stage for providing an output of the pipeline structure. At least one intermediate stage is interposed between the first stage and the last stage. The pipeline structure also includes a phase shifting circuit for generating at least one local clock signal for controlling the at least one intermediate stage. The first stage and the last stage are controlled by a main clock signal, the at least one local clock signal is generated from the main clock signal, and the main clock signal and the at least one local clock signal are out of phase. Also provided is a method of operating a pipeline structure that includes stages arranged in a sequence.

Abstract translation: 提供了一种用于数字系统的管道结构。 流水线结构包括以从第一阶段顺序排列的阶段，用于接收流水线结构的输入到用于提供流水线结构的输出的最后阶段。 在第一阶段和最后阶段之间插入至少一个中间阶段。 流水线结构还包括一个移相电路，用于产生至少一个本地时钟信号用于控制至少一个中间级。 第一级和最后级由主时钟信号控制，从主时钟信号产生至少一个本地时钟信号，并且主时钟信号和至少一个本地时钟信号异相。 还提供了一种操作流水线结构的方法，其包括按顺序排列的阶段。