公开(公告)号：US20040135908A1

公开(公告)日：2004-07-15

申请号：US10696396

申请日：2003-10-29

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Alessandro Capra ,  Massimo Mancuso ,  Herve Broquin ,  Paolo Antonino Fodera ,  Elena Salurso

IPC: H04N005/335

CPC classification number: H04N1/648

Abstract: Digital video signals, such as the signals generated by an image sensor in a Bayer format, are converted into an encoded format. In the Bayer format, the pixels of each line are alternately coded with two colors, and then converted into the encoded format. In the encoded format, the pixels of the digital video signals are reordered into sets of adjacent pixels, such that the sets group pixels coded with the same color. The encoded signal data results in a reduced switching activity when transmitted over a bus.

Abstract translation: 诸如由拜耳格式的图像传感器产生的信号的数字视频信号被转换成编码格式。 在拜耳格式中，每行的像素被交替地用两种颜色编码，然后被转换为编码格式。 在编码格式中，将数字视频信号的像素重新排列成相邻像素的集合，使得组合像素以相同颜色编码。 编码的信号数据在总线上传输时导致切换活动降低。

公开(公告)号：US20040202244A1

公开(公告)日：2004-10-14

申请号：US10757368

申请日：2004-01-13

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Agatino Pennisi

IPC: H04B001/66

CPC classification number: G06F13/423 ,  Y02D10/14 ,  Y02D10/151

Abstract: N binary signals are transmitted through a bus of m leads, where m

Abstract translation: 通过在第二信号上对第一信号进行编码，以一串时钟脉冲的节奏通过m引线的总线m

公开(公告)号：US20040019814A1

公开(公告)日：2004-01-29

申请号：US10440044

申请日：2003-05-16

Applicant: STMicroelectronics SA ,  STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Luigi Mantellassi

IPC: G06F001/26

CPC classification number: G06F9/30101 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  H01L23/34 ,  H01L2924/0002 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  H01L2924/00

Abstract: A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

Abstract translation: 片上系统（SoC）架构包括多个块，每个块包括功率控制模块，用于选择性地控制由该块所耗散的功率。 对于每个块，提供功率寄存器以接收功率控制指令以选择性地控制相应的功率控制模块。 该系统还包括用于将各个功率控制指令写入块的功率控制寄存器的功率控制单元，由此在功率控制单元的集中控制下，对每个块单独且独立地控制功率消耗。 对于每个块，还提供功率状态寄存器以接收关于相应块内的功率控制的状态信息。 电源控制单元从这些电源状态寄存器读取状态指令。

公开(公告)号：US20020035679A1

公开(公告)日：2002-03-21

申请号：US09998568

申请日：2001-11-16

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Davide Tesi ,  Francesco Nino Mammoliti ,  Francesco Bombaci

IPC: G06F009/00

CPC classification number: G06F9/30181 ,  G06F9/30003 ,  G06F9/30145

Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For at least one of the instructions, the operand section represents operation control signals of the processor. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Abstract translation: 处理器设置有一组通常由操作部分和操作数部分形成的指令。 对于至少一个指令，操作数部分表示处理器的操作控制信号。 以这种方式，可以实现该组指令的扩展，以便根据用户自己的要求定制指令集。 因此，处理器控制单元应该能够在接收到一个这样的指令时将其输出耦合到其输入，从而在没有解释的情况下传送这样的内部操作控制信号。

公开(公告)号：US20040103334A1

公开(公告)日：2004-05-27

申请号：US10622835

申请日：2003-07-18

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Francesco Pappalardo ,  Agatino Pennisi

IPC: G06F001/12

CPC classification number: G06F1/06 ,  G06F9/3869

Abstract: A pipeline structure is provided for use in a digital system. The pipeline structure includes stages arranged in a sequence from a first stage for receiving an input of the pipeline structure to a last stage for providing an output of the pipeline structure. At least one intermediate stage is interposed between the first stage and the last stage. The pipeline structure also includes a phase shifting circuit for generating at least one local clock signal for controlling the at least one intermediate stage. The first stage and the last stage are controlled by a main clock signal, the at least one local clock signal is generated from the main clock signal, and the main clock signal and the at least one local clock signal are out of phase. Also provided is a method of operating a pipeline structure that includes stages arranged in a sequence.

Abstract translation: 提供了一种用于数字系统的管道结构。 流水线结构包括以从第一阶段顺序排列的阶段，用于接收流水线结构的输入到用于提供流水线结构的输出的最后阶段。 在第一阶段和最后阶段之间插入至少一个中间阶段。 流水线结构还包括一个移相电路，用于产生至少一个本地时钟信号用于控制至少一个中间级。 第一级和最后级由主时钟信号控制，从主时钟信号产生至少一个本地时钟信号，并且主时钟信号和至少一个本地时钟信号异相。 还提供了一种操作流水线结构的方法，其包括按顺序排列的阶段。