公开(公告)号：US11537840B2

公开(公告)日：2022-12-27

申请号：US16189264

申请日：2018-11-13

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Danilo Pietro Pau ,  Emanuele Plebani ,  Fabio Giuseppe De Ambroggi ,  Floriana Guido ,  Angelo Bosco

IPC: G06N3/04 ,  G06N3/08 ,  G06N5/00 ,  G06N3/063

Abstract: A neural network classifies an input signal. For example, an accelerometer signal may be classified to detect human activity. In a first convolutional layer, two-valued weights are applied to the input signal. In a first two-valued function layer coupled at input to an output of the first convolutional layer, a two-valued function is applied. In a second convolutional layer coupled at input to an output of the first two-valued functional layer, weights of the second convolutional layer are applied. In a fully-connected layer coupled at input to an output of the second convolutional layer, two-valued weights of the fully connected layer are applied. In a second two-valued function layer coupled at input to an output of the fully connected layer, a two-valued function of the second two-valued function layer is applied. A classifier classifies the input signal based on an output signal of second two-valued function layer.

公开(公告)号：US12164883B2

公开(公告)日：2024-12-10

申请号：US17203591

申请日：2021-03-16

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Xiao Kang Jiao ,  Fabio Giuseppe De Ambroggi ,  Loris Luise

IPC: G06F7/544 ,  G06F3/06 ,  H03H17/06 ,  H03M1/12

Abstract: A method includes retrieving a plurality of datasets from respective memory registers of a memory and storing the retrieved plurality of datasets in respective register portions of a first register. A dataset of data-processing coefficients are stored in a second register. First processing is applied using, as the first operand, a first sub-set of dataset elements stored in the first register, and using, as the second operand, the data-processing coefficients, obtaining a first result. Second processing is applied using, as the first operand, a second sub-set of dataset elements stored in the first register comprised in a second window having a size equal to the dataset size, and using, as the second operand, the replica of the dataset of data-processing coefficients, obtaining a second result. An output is generated based on the first and second results. The first and second processing may perform multiply accumulate (MAC) operations.

公开(公告)号：US12118451B2

公开(公告)日：2024-10-15

申请号：US15423272

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Giuseppe Desoli ,  Thomas Boesch ,  Nitin Chawla ,  Surinder Pal Singh ,  Elio Guidetti ,  Fabio Giuseppe De Ambroggi ,  Tommaso Majo ,  Paolo Sergio Zambotti

IPC: G06N3/04 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/0464 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78 ,  G06F115/02 ,  G06F115/08 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

CPC classification number: G06N3/0464 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/44505 ,  G06F13/4022 ,  G06F15/7817 ,  G06F2115/02 ,  G06F2115/08 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

Abstract: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.

公开(公告)号：US11630671B1

公开(公告)日：2023-04-18

申请号：US17581601

申请日：2022-01-21

Applicant: STMICROELECTRONICS (BEIJING) R&D CO., LTD. ,  STMICROELECTRONICS S.r.l.

Inventor： Xiao Kang Jiao ,  Fabio Giuseppe De Ambroggi

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/355

Abstract: A device includes a circular buffer, which, in operation, is organized into a plurality of subsets of buffers, and control circuitry coupled to the circular buffer. The control circuitry, in operation, receives a memory load command to load a set of data into the circular buffer. The memory load command has an offset parameter indicating a data offset and a subset parameter indicating a subset of the plurality of subsets into which the circular buffer is organized. The control circuitry responds to the command by identifying a set of buffer addresses of the circular buffer based on a value of the offset parameter and a value of the subset parameter, and loading the set of data into the circular buffer using the identified set of buffer addresses.