公开(公告)号：US20240162175A1

公开(公告)日：2024-05-16

申请号：US18054806

申请日：2022-11-11

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Lucrezia GUARINO ,  Francesca MILANESI ,  Claudio ZAFFERONI

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/0225 ,  H01L2224/0233 ,  H01L2224/03001 ,  H01L2224/0401 ,  H01L2224/04042

Abstract: The present disclosure is directed to embodiments of a conductive structure on a conductive barrier layer that separates the conductive structure from a conductive layer on which the conductive barrier layer is present. A gap or crevice extends along respective surfaces of the conductive structure and along respective surfaces of one or more insulating layers. The gap or crevice separates the respective surfaces of the one or more insulating layers from the respective surfaces of the conductive structure. The gap or crevice provides clearance in which the conductive structure may expand into when exposed to changes in temperature. For example, when coupling a wire bond to the conductive structure, the conductive structure may increase in temperature and expand into the gap or crevice. However, even in the expanded state, respective surfaces of the conductive structure do not physically contact the respective surfaces of the one or more insulating layers.

公开(公告)号：US20190035741A1

公开(公告)日：2019-01-31

申请号：US16048123

申请日：2018-07-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Samuele SCIARRILLO ,  Ivan VENEGONI ,  Paolo COLPANI ,  Francesca MILANESI

IPC: H01L23/532 ,  H01L23/538 ,  H01L23/31 ,  H01L21/768 ,  H01L23/528 ,  H01L21/308

Abstract: A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.

公开(公告)号：US20240088012A1

公开(公告)日：2024-03-14

申请号：US17941886

申请日：2022-09-09

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Francesca MILANESI ,  Paolo COLPANI

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49861 ,  H01L21/76834

Abstract: The present disclosure is directed to embodiments of a conductive structure on a conductive layer, which may be a conductive damascene layer of a semiconductor device or package. The conductive damascene layer may be within a substrate of the semiconductor device or package. A crevice is present between one or more sidewalls of the conductive structure and one or more sidewalls of one or more insulating layers on the substrate and extends to a surface of the conductive layer. A sealing layer is formed in the crevice that seals the conductive layer from moisture and contaminants external to the semiconductor device or package that may enter the crevice. In other words, the sealing layer stops the moisture and contaminants from reaching the conductive layer such that the conductive layer does not corrode due to exposure to the moisture and contaminants.