公开(公告)号：US20230135498A1

公开(公告)日：2023-05-04

申请号：US18050413

申请日：2022-10-27

Applicant: STMICROELECTRONICS S.r.l. ,  SHENZHEN STS MICROELECTRONICS CO., LTD.

Inventor： Yi Ming LIANG ,  Roberto TIZIANI ,  Qian LIU ,  Feng DING

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/00 ,  H01L23/373

Abstract: Embodiments of the present disclosure relate to a semiconductor package, a method of forming the package and an electronic device. For example, the semiconductor package may comprise a first substrate assembly comprising a first surface and a second surface opposite the first surface. The semiconductor package may also comprise one or more chips connected or coupled to the first surface of the first substrate assembly by a first thermally and electrically conductive connecting material. In addition, the semiconductor package further comprises a second substrate assembly comprising a third surface and a fourth surface opposite the third surface, the third surface and the first surface being arranged to face each other, and the third surface being connected to one or more chips by a second thermally and electrically conductive connecting material. At least one of the first surface and the third surface is shaped to have a stepped pattern to match a surface of the one or more chips. Embodiments of the present disclosure may at least simplify the double-sided heat dissipation structure and improve the heat dissipation effect of the chip.

公开(公告)号：US20240363501A1

公开(公告)日：2024-10-31

申请号：US18634663

申请日：2024-04-12

Applicant: Shenzhen STS Microelectronics Co., Ltd ,  STMicroelectronics International N.V.

Inventor： Qian LIU ,  Roberto TIZIANI

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49562 ,  H01L23/3675 ,  H01L23/49531 ,  H01L24/29 ,  H01L24/37 ,  H01L25/0652 ,  H01L2224/29005 ,  H01L2224/29022 ,  H01L2224/3702 ,  H01L2224/37147 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/13091

Abstract: Embodiments of the present disclosure relate to a semiconductor package, a method of forming semiconductor package and a power module. For example, there is provided a semiconductor package. The semiconductor package may comprise a chip level having a first side and a second side opposite to the first side, wherein the chip level comprises a plurality of power transistors and each power transistor is provided with a source and a gate at the first side. Besides, the semiconductor package may also comprise a first conductive level positioned on the first side and comprising a gate connection portion electrically connected with the gate and a source connection portion electrically connected with the source. The semiconductor package further comprises a second conductive level comprising a gate lead-out portion electrically connected with the gate connection portion and a source lead-out portion electrically connected with the source connection portion, wherein the first conductive level is positioned between the second conductive level and the chip level. Embodiments of the present disclosure may enhance the working performance of the product by improving consistency of conductive paths from the gate and the source of each power transistor to corresponding points.