公开(公告)号：US20160233258A1

公开(公告)日：2016-08-11

申请号：US14923799

申请日：2015-10-27

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Axel CROCHERIE ,  Jean-Pierre ODDOU ,  Stéphane ALLEGRET-MARET ,  Hugues LEININGER

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/14607 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685

Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.

Abstract translation: 包括像素阵列的彩色图像传感器形成在具有接收照明的背面的半导体层中。 绝缘导电壁从背面渗入半导体层并将像素彼此分开。 对于每个像素，彩色像素从背面渗入半导体层的厚度的5至30％，并且占据由壁限定的表面积的至少90％。 导电层从过滤器的侧壁一直延伸到壁。

公开(公告)号：US20230263082A1

公开(公告)日：2023-08-17

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck ARNAUD ,  David GALPIN ,  Stephane ZOLL ,  Olivier HINSINGER ,  Laurent FAVENNEC ,  Jean-Pierre ODDOU ,  Lucile BROUSSOUS ,  Philippe BOIVIN ,  Olivier WEBER ,  Philippe BRUN ,  Pierre MORIN

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/882 ,  H10N70/8265 ,  H10N70/8413 ,  G11C2013/008

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US20190140176A1

公开(公告)日：2019-05-09

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck ARNAUD ,  David GALPIN ,  Stephane ZOLL ,  Olivier HINSINGER ,  Laurent FAVENNEC ,  Jean-Pierre ODDOU ,  Lucile BROUSSOUS ,  Philippe BOIVIN ,  Olivier WEBER ,  Philippe BRUN ,  Pierre MORIN

IPC: H01L45/00 ,  H01L27/24

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.