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公开(公告)号：US09601382B2
公开(公告)日：2017-03-21
申请号：US14940325
申请日：2015-11-13
Inventor： Stephane Monfray , Ronald K. Sampson , Nicolas Loubet
IPC: H01L21/336 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/84 , H01L29/10 , H01L29/165 , H01L29/06
CPC classification number: H01L21/823431 , H01L21/02164 , H01L21/0217 , H01L21/02529 , H01L21/02532 , H01L21/02573 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L21/845 , H01L29/0673 , H01L29/1083 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.
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公开(公告)号：US09601381B2
公开(公告)日：2017-03-21
申请号：US14097565
申请日：2013-12-05
Inventor： Nicolas Loubet , Stephane Monfray , Ronald Kevin Sampson
IPC: H01L27/088 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/84 , H01L29/10 , H01L29/165 , H01L29/06
CPC classification number: H01L21/823431 , H01L21/02164 , H01L21/0217 , H01L21/02529 , H01L21/02532 , H01L21/02573 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L21/845 , H01L29/0673 , H01L29/1083 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer. Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.
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公开(公告)号：US20160071772A1
公开(公告)日：2016-03-10
申请号：US14940325
申请日：2015-11-13
Inventor： Stephane Monfray , Ronald K. Sampson , Nicolas Loubet
IPC: H01L21/8234 , H01L29/165 , H01L29/10 , H01L29/78 , H01L21/84 , H01L21/02
CPC classification number: H01L21/823431 , H01L21/02164 , H01L21/0217 , H01L21/02529 , H01L21/02532 , H01L21/02573 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L21/845 , H01L29/0673 , H01L29/1083 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.
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4.发明申请METHOD FOR THE FORMATION OF A FINFET DEVICE WITH EPITAXIALLY GROWN SOURCE-DRAIN REGIONS HAVING A REDUCED LEAKAGE PATH 有权形成具有减少渗漏路径的外来源岩源区的FINFET装置的方法公开(公告)号：US20150162433A1
公开(公告)日：2015-06-11
申请号：US14097565
申请日：2013-12-05
Inventor： Nicolas Loubet , Stephane Monfray , Ronald Kevin Sampson
IPC: H01L29/78 , H01L29/16 , H01L29/165 , H01L29/66
CPC classification number: H01L21/823431 , H01L21/02164 , H01L21/0217 , H01L21/02529 , H01L21/02532 , H01L21/02573 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L21/845 , H01L29/0673 , H01L29/1083 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.
Abstract translation: 第一半导体材料的细长散热片与下层基底层（SOI或本体型）绝缘和形成。 然后形成第二半导体材料的细长的栅极，以在沟道区域上跨过细长的翅片，并且栅极侧壁被侧壁间隔物覆盖。 提供保护材料以覆盖下面的基底层并且在细长门之间限定细长翅片的侧壁上的侧壁间隔物。 位于保护材料侧壁间隔件（但不在细长门下）的细长翅片的第一半导体材料和绝缘材料被去除以形成与沟道区域对准的沟槽。 然后在细长门之间的每个沟槽内外延生长另外的半导体材料，以形成邻近由位于细长栅极下方的第一半导体材料的细长鳍片形成的沟道区域的源极 - 漏极区域。
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公开(公告)号：US11378827B2
公开(公告)日：2022-07-05
申请号：US17083525
申请日：2020-10-29
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Frédéric Boeuf
Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.
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Patent Agency Ranking
公开(公告)号：US10795189B2
公开(公告)日：2020-10-06
申请号：US16247096
申请日：2019-01-14
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray
Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.
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公开(公告)号：US10690947B2
公开(公告)日：2020-06-23
申请号：US16254753
申请日：2019-01-23
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Frédéric Boeuf
Abstract: In one aspect, a photonic device includes a first region having a first doping type, where the first region is divided into an upper portion made of silicon-germanium and a lower portion made of silicon. The device further includes a second region having a second doping type. The first region and the second region contact to form a vertical PN junction.
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公开(公告)号：US10103310B2
公开(公告)日：2018-10-16
申请号：US14851536
申请日：2015-09-11
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Emmanuel Dubois , Jean-Francois Robillard , Stephane Monfray , Thomas Skotnicki
Abstract: A thermo-electric generator includes a semiconductor membrane with a phononic structure containing at least one P-N junction. The membrane is suspended between a first support designed to be coupled to a cold thermal source and a second support designed to be coupled to a hot thermal source. The structure for suspending the membrane has an architecture allowing the heat flux to be redistributed within the plane of the membrane.
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公开(公告)号：US09698707B2
公开(公告)日：2017-07-04
申请号：US14455110
申请日：2014-08-08
Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Stephane Monfray , Arthur Arnaud , Thomas Skotnicki , Onoriu Puscasu , Sebastien Boisseau
CPC classification number: H02N10/00 , F03G7/06 , H02N1/08 , H02N2/18 , Y10T29/4913
Abstract: A device for converting thermal power into electric power includes many conversion cells arranged inside and on top of a substrate. Each conversion cell includes a curved bimetal strip and first and second diodes coupled to the bimetal strip. The diodes are arranged in a semiconductor region of the substrate.
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公开(公告)号：US20170169696A1
公开(公告)日：2017-06-15
申请号：US15139500
申请日：2016-04-27
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Christophe Maitre , Thomas Skotnicki
IPC: G08B21/18 , G01K1/02 , H01L41/113
CPC classification number: G08B21/182 , G01D21/00 , G01K1/024 , G01K5/72 , G01P15/02 , H01L41/113 , H02N2/18
Abstract: A detector of an event includes an electrical energy generator formed by a flexible piezoelectric element with a weight fastened to the flexible piezoelectric element that is biased with the weight in a position with the piezoelectric element flexed. In response to detection of the event, a trigger releases the weight so as to cause a vibration of the piezoelectric element. This vibration is converted by the flexible piezoelectric element into electrical energy. An electronic system is power by the electrical energy and is operable to generate an electrical signal indicative of the detected event.
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