公开(公告)号：US20020074607A1

公开(公告)日：2002-06-20

申请号：US10077288

申请日：2002-02-15

Applicant: STMicroelectronics, S.r.I.

Inventor： Loris Vendrame ,  Paolo Ghezzi

IPC: H01L029/94

CPC classification number: H01L29/0692 ,  H01L21/8249 ,  H01L29/7322

Abstract: A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor. The bipolar transistor includes: a buried semiconductor layer having a second type of conductivity placed at a prescribed depth from the surface of said bipolar transistor, an isolation semiconductor region having the second type of conductivity, in direct contact with said buried semiconductor layer, and suitable for delimiting a portion of said substrate, forming a base region; an emitter region formed within said base region having the second type of conductivity, a base contact region of said transistor formed within said base region having the first type of conductivity, a collector contact region formed within said isolation semiconductor region having the second type of conductivity, wherein said base region has a doping concentration between 1016 and 1017 atoms/cm3.

Abstract translation: 双极晶体管是通过制造CMOS非易失性存储器件的工艺生产的，并且是集成电路的一部分。 集成电路包括具有第一导电类型的半导体衬底，形成在所述衬底中的PMOS晶体管，形成在所述衬底中的NMOS晶体管和双极晶体管。 所述双极晶体管包括：具有从所述双极晶体管的表面设置在规定深度的第二导电类型的掩埋半导体层，具有与所述掩埋半导体层直接接触的第二导电类型的隔离半导体区域， 用于限定所述衬底的一部分，形成基部区域; 形成在具有第二导电类型的所述基极区内的发射极区域，形成在具有第一导电类型的所述基极区域内的所述晶体管的基极接触区域，形成在具有第二导电类型的所述隔离半导体区域内的集电极接触区域 ，其中所述碱性区域的掺杂浓度为1016至1017原子/ cm3。

公开(公告)号：US20040061168A1

公开(公告)日：2004-04-01

申请号：US10606164

申请日：2003-06-25

Applicant: STMICROELECTRONICS S.r.I

Inventor： Paolo Cappelletti ,  Paolo Ghezzi ,  Alfonso Maurelli ,  Loris Vendrame ,  Paola Zabberoni

IPC: H01L029/788

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

Abstract: An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

Abstract translation: 提供电可擦除和可编程的存储单元。 存储单元包括浮置栅极MOS晶体管和用于将电荷注入浮置栅极的双极晶体管。 浮置栅极晶体管具有形成在第一阱中的源极区和漏极区，沟道限定在漏极和源极区之间，控制栅极区以及在沟道和控制栅极区上延伸的浮动栅极。 双极晶体管具有形成在第一阱中的发射极区域，由第一阱构成的基极区域和由沟道组成的集电极区域。 存储单元包括与第一阱绝缘的第二阱，并且控制栅区形成在第二阱中。 本发明的另外的实施例提供了包括至少一个这样的存储单元的存储器，包括这种存储器的电子设备，以及集成存储器单元和擦除存储器单元的方法。