公开(公告)号：US20040268275A1

公开(公告)日：2004-12-30

申请号：US10850834

申请日：2004-05-21

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Cappelletti ,  Alfonso Maurelli

IPC: H01L021/44 ,  G06F017/50

CPC classification number: H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.

Abstract translation: 测试芯片执行测量以评估互连的性能。 特别地，测量统计失效分布，电迁移和漏电流。 算法检测任何可用的n个金属层的通孔故障。 测试芯片包括ROM存储器阵列。 要测量的通孔在阵列的列中形成。 通过强制通过阵列列和参考列的预定电流来检测通过或接触故障。 通过比较所得的电压降来获得故障分析。

公开(公告)号：US20040061168A1

公开(公告)日：2004-04-01

申请号：US10606164

申请日：2003-06-25

Applicant: STMICROELECTRONICS S.r.I

Inventor： Paolo Cappelletti ,  Paolo Ghezzi ,  Alfonso Maurelli ,  Loris Vendrame ,  Paola Zabberoni

IPC: H01L029/788

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

Abstract: An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

Abstract translation: 提供电可擦除和可编程的存储单元。 存储单元包括浮置栅极MOS晶体管和用于将电荷注入浮置栅极的双极晶体管。 浮置栅极晶体管具有形成在第一阱中的源极区和漏极区，沟道限定在漏极和源极区之间，控制栅极区以及在沟道和控制栅极区上延伸的浮动栅极。 双极晶体管具有形成在第一阱中的发射极区域，由第一阱构成的基极区域和由沟道组成的集电极区域。 存储单元包括与第一阱绝缘的第二阱，并且控制栅区形成在第二阱中。 本发明的另外的实施例提供了包括至少一个这样的存储单元的存储器，包括这种存储器的电子设备，以及集成存储器单元和擦除存储器单元的方法。

公开(公告)号：US20030235097A1

公开(公告)日：2003-12-25

申请号：US10449761

申请日：2003-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Emilio Camerlenghi ,  Paolo Cappelletti ,  Tecla Ghilardi ,  Mauro Sali ,  Giorgio Servalli

IPC: G11C007/00

CPC classification number: G11C29/006 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

Abstract: An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.

Abstract translation: 集成的非易失性存储器件可以包括组织成行（或字线）和列（或位线），对应的行和列解码电路的存储器单元的第一矩阵，以及用于读取和修改数据的读取，修改和擦除电路 存储在存储单元中。 此外，存储器件还可以包括测试结构，其包括小于第一存储器单元的存储器单元的第二矩阵。 第二存储器矩阵可以包括每个具有与栅极距离的不同接触的字线耦合。 也就是说，每个联轴器与相应的门相比不同于相邻联接器的距离。